SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The SSI can generate interrupts when the following conditions are observed:
All interrupt events are ORed together before sent to the event fabric, so the SSI generates a single interrupt request to the controller regardless of the number of active interrupts. The TX FIFO, RX FIFO, RX time-out, and RX overrun interrupts can be masked by clearing the appropriate bit in the SSI:IMSC register. Setting the appropriate mask bit in the SSI:IMSC register enables the interrupt. RX DMA done and TX DMA done interrupts can be masked by setting the appropriate bit in the UDMA Channel Request Done Mask register (UDMA:DONEMASK). Clearing the appropriate bit in the UDMA:DONEMASK register enables the RX or TX DMA done interrupt.
The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status register (SSI:RIS) and the SSI Masked Interrupt Status register (SSI:MIS) (see Section 23.7.1).
The receive FIFO service interrupt request SSI:RIS.RXRIS is asserted when there are four or more valid entries in the receive FIFO.
The transmit FIFO service interrupt request SSI:RIS.TXRIS is asserted when there are four or fewer valid entries in the transmit FIFO. The transmitter interrupt is not qualified with the SSP enable signal, which allows data to be written to the transmit FIFO before enabling the SSP and the interrupts and allows the SSP and interrupts to be enabled so that data can be written to the transmit FIFO by an interrupt service routine (ISR).
The receive overrun interrupt SSI:RIS.RORRIS request is asserted when the FIFO is already full and an additional data frame is received, causing an overrun of the FIFO. Data is overwritten in the receive shift register, but not in the FIFO.
The RX FIFO has a time-out period of 32 periods at the rate of SSIn_CLK (whether or not SSIn_CLK is currently active), and is started when the RX FIFO goes from empty to not empty. If the RX FIFO is emptied before 32 clocks pass, the time-out period is reset. As a result, the ISR clears the RX FIFO time-out interrupt just after reading out the RX FIFO by setting the RTIC bit in the SSI Interrupt Clear SSI:ICR register to 1.
The interrupt must not be cleared so late that the ISR returns before the interrupt is actually cleared, or the ISR may be reactivated unnecessarily.