SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
With each data request from the crypto engine, the DMAC requests a transfer from the AHB master. The transfer size is at most the block size of the corresponding algorithm. This block size depends on the selected algorithm in the master control module.
Table 13-2 provides a summary of the supported DMAC operations. The module refers to the selected module in the master control module. In Table 13-2, the TAG enabled label indicates that the TAG bit is set in the master control configuration register.
| Module | Incoming Data Stream (for Channel 0) | Outcoming Data Stream (for Channel 1) | ||
|---|---|---|---|---|
| Source | Destination | Source | Destination | |
| Key store | External memory location | Key store RAM | – | – |
| Crypto | RAM (Authentication data only) | AES | See (1) | See (1) |
| External memory location | AES | AES | External memory location | |
| See (2) | See (2) | AES (TAG enabled) | External memory location | |
| Hash | External memory location | SHA-2 (TAG disabled) | See (1) | See (1) |
| See (2) | See (2) | SHA-2 (TAG enabled) | External memory location | |
| External memory location | SHA-2 (TAG disabled) | SHA-2 (TAG enabled) | External memory location | |