Internal audio clock source must be selected for both the I2S module and the PRCM module:
- I2S:AIFWCLKSRC = 2
- PRCM:I2SBCLKSEL.SRC = 1
The setting for the PRCM:I2SCLKCTL.SMPL_ON_POSEDGE register specifies on which edge of BCLK the WCLK signal shall be sampled. This setting must be equal to the setting for the I2S:AIFFMTCFG.SMPL_EDGEregister.
The MCLK, BCLK, WCLK frequencies, and WCLK duty cycle are configured as follows:
- MCLK frequency = 48 MHz / PRCM:I2SMCLKDIV.MDIV
- BCLK frequency = 48 MHz / PRCM:I2SBCLKDIV.BDIV
- For WCLK the configuration depends on the duty cycle (PRCM:I2SWCLKDIV.WDIV is referred to as WDIV):
- Single phase (DSP format): PRCM:I2SCLKCTL.WCLK_PHASE = 0
- WCLK is high for 1 BCLK period and low for WDIV[9:0] (1 to 1023) BCLK periods.
- WCLK frequency = BCLK frequency / (1 + PRCM:I2SWCLKDIV.WDIV[9:0])
- Dual phase (I2S, LJF, and RJF formats): PRCM:I2SCLKCTL.WCLK_PHASE = 1
- WCLK is high for WDIV[9:0] (1 to 1023) BCLK periods and low for WDIV[9:0] (1 to 1023) BCLK periods.
- WCLK frequency = BCLK frequency / (2 × WDIV[9:0])
- User-defined: PRCM:I2SCLKCTL.WCLK_PHASE = 2
- WCLK is high for WDIV[7:0] (1 to 255) BCLK periods and low for WDIV[15:8] (1 to 255) BCLK periods.
- WCLK frequency = BCLK frequency / (WDIV[7:0] + WDIV[15:8])
The signal generation of the clock signals MCLK, BCLK, and WCLK must be enabled by setting PRCM:I2SCLKCTL.EN = 1. The MCLK, BCLK, and WCLK signals are static low when PRCM:I2SCLKCTL.EN = 0.