SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The prescaler optionally divides the Timer2 clock. The divided clock determines the:
AUX_TIMER2:PRECFG.CLKDIV sets the division. Division ranges from 1 to 256. Registers are accessed at the Timer2 clock.