SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The register configuration follows:
DATA_DELAY + (WORD_LEN × channel count) must be equal to or less than the number of BCLK periods per phase.
The channel count is determined by the MSB set in the I2S:AIFWMASK0 and I2S:AIFWMASK1 registers.