SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
The μDMA controller responds to two types of requests from a peripheral: single request or burst request. Each peripheral may support either or both types of requests. A single request means that the peripheral is ready to transfer one item, while a burst request means that the peripheral is ready to transfer multiple items.
The μDMA controller responds differently depending on whether the peripheral is making a single request or a burst request. If both types of requests are asserted and the μDMA channel has been set up for a burst transfer, then the burst request takes precedence. Table 15-2 lists how each peripheral supports the two request types.
| Peripheral | Single Request Signal | Burst Request Signal |
|---|---|---|
| ADC | None (FIFO is not empty) | Sequencer IE bit (FIFO is half full) |
| General-purpose timer | Raw interrupt pulse | None |
| GPIO | Raw interrupt pulse | None |
| SSI TX | TX FIFO not full | TX FIFO level (fixed at 4) |
| SSI RX | RX FIFO not empty | RX FIFO level (fixed at 4) |
| UART TX | TX FIFO not full | TX FIFO level (configurable) |
| UART RX | RX FIFO not empty | RX FIFO level (configurable) |