SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
Table 13-17 shows the performance of the AES module running at 200 MHz for DMA-based cryptographic operations.
Performance in Mbps at 200 MHz | ||||
---|---|---|---|---|
Crypto Mode | Raw Engine Performance | 1-Block Packet Performance(1) | 20-Block Performance(1) | 100-Block Performance(1) |
AES-128 (1 block = 128 bits) | ||||
AES-128-ECB | 492 | 111 | 420 | 476 |
AES-128-CBC | 483 | 104 | 408 | 466 |
AES-128-CTR | 492 | 104 | 415 | 474 |
AES-128-GCM(2) | 492 | 77 | 382 | 459 |
AES-192 (1 block = 128 bits) | ||||
AES-192-ECB | 412 | 107 | 361 | 401 |
AES-192-CBC | 406 | 100 | 352 | 394 |
AES-192-CTR | 412 | 100 | 357 | 400 |
AES-192-GCM(2) | 412 | 73 | 330 | 388 |
AES-256 (1 block = 128 bits) | ||||
AES-256-ECB | 355 | 102 | 316 | 347 |
AES-256-CBC | 350 | 96 | 309 | 341 |
AES-256-CTR | 355 | 96 | 313 | 346 |
AES-256-GCM(2) | 355 | 63 | 291 | 336 |
Hash (SHA-256: 1 block = 512 bits; SHA-512: 1 block = 1024 bits) | ||||
SHA-256 | 1575 | 375 | 1358 | 1526 |
SHA-512 | 2528 | 671 | 2221 | 2460 |
The engine performance depends heavily on the number of blocks processed per operation. Processing a single block results in the minimum engine performance; in this case, the configuration overhead is the most significant (assuming the engine is fully reconfigured for each operation). Therefore, processing multiple blocks per operation results in a significantly higher performance.