SWCU192 November 2021 CC1312R7 , CC1352P7 , CC2652P7 , CC2652R7
AON_PMCTL supports MCU_VD with a clock that is divided and gated by PRCM before being distributed to all modules in MCU_VD. Figure 8-6 shows the registers in PRCM that define division and gate control for all module clocks. When no BUS transactions can occur, hardware automatically gates the SYSBUS clock.
The following conditions must be true to gate the SYSBUS:
The SYSBUS clock may run even when the system CPU is in deep sleep mode when either DMA, SEC, I2S, or RFCORE requires an active interconnect.
MCU_AON has two clocks, an INFRASTRUCTURE clock that always runs and a PERBUSULL clock that is identical to the INFRASTRUCTURE clock whenever the SYSBUS clock is running. When the SYSBUS clock is gated, the PERBUSULL clock is automatically gated. INFRASTRUCTURE and PERBUSULL clocks are automatically controlled to run at a maximum of half the clock frequency of SCLK_HF, regardless of the settings in PRCM:INFCLKDIVR.RATIO, PRCM:INFCLKDIVS.RATIO, or PRCM:INFCLKDIVDS.RATIO.