SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5
Table 2-72 lists the memory-mapped registers for the NVIC registers. All register offset addresses not listed in Table 2-72 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
100h | ISER | Interrupt Set-Enable Register | Go |
180h | ICER | Interrupt Clear-Enable Register | Go |
200h | ISPR | Interrupt Set-Pending Register | Go |
280h | ICPR | Interrupt Clear-Pending Register | Go |
400h | IPR0 | Interrupt Priority Register 0 | Go |
404h | IPR1 | Interrupt Priority Register 1 | Go |
408h | IPR2 | Interrupt Priority Register 2 | Go |
40Ch | IPR3 | Interrupt Priority Register 3 | Go |
410h | IPR4 | Interrupt Priority Register 4 | Go |
414h | IPR5 | Interrupt Priority Register 5 | Go |
418h | IPR6 | Interrupt Priority Register 6 | Go |
41Ch | IPR7 | Interrupt Priority Register 7 | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-73 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
ISER is shown in Table 2-74.
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Interrupt Set-Enable Register
Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SETENA | R/W | 0h | Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields. |
ICER is shown in Table 2-75.
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Interrupt Clear-Enable Register
Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLRENA | R/W | 0h | Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field. |
ISPR is shown in Table 2-76.
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Interrupt Set-Pending Register
Use the Interrupt Set-Pending Register to force interrupts into the pending state and determine which interrupts are currently pending
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SETPEND | R/W | 0h | Interrupt set-pending bits for a: Write: 1 = pend interrupt 0 = no effect Read: 1 = interrupt is pending 0 = interrupt is not pending. |
ICPR is shown in Table 2-77.
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Interrupt Clear-Pending Register
Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLRPEND | R/W | 0h | Interrupt clear-pending bits: Write: 1 = clear interrupt pending bit, 0 = no effect Read: 1 = interrupt is pending 0 = interrupt is not pending. |
IPR0 is shown in Table 2-78.
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Interrupt Priority Register 0
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_3 | R/W | 0h | Priority of interrupt 3 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_2 | R/W | 0h | Priority of interrupt 2 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_1 | R/W | 0h | Priority of interrupt 1 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_0 | R/W | 0h | Priority of interrupt 0 |
5-0 | RESERVED | R | 0h | Reserved |
IPR1 is shown in Table 2-79.
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Interrupt Priority Register 1
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_7 | R/W | 0h | Priority of interrupt 7 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_6 | R/W | 0h | Priority of interrupt 6 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_5 | R/W | 0h | Priority of interrupt 5 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_4 | R/W | 0h | Priority of interrupt 4 |
5-0 | RESERVED | R | 0h | Reserved |
IPR2 is shown in Table 2-80.
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Interrupt Priority Register 2
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_11 | R/W | 0h | Priority of interrupt 11 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_10 | R/W | 0h | Priority of interrupt 10 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_9 | R/W | 0h | Priority of interrupt 9 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_8 | R/W | 0h | Priority of interrupt 8 |
5-0 | RESERVED | R | 0h | Reserved |
IPR3 is shown in Table 2-81.
Return to the Summary Table.
Interrupt Priority Register 3
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_15 | R/W | 0h | Priority of interrupt 15 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_14 | R/W | 0h | Priority of interrupt 14 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_13 | R/W | 0h | Priority of interrupt 13 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_12 | R/W | 0h | Priority of interrupt 12 |
5-0 | RESERVED | R | 0h | Reserved |
IPR4 is shown in Table 2-82.
Return to the Summary Table.
Interrupt Priority Register 4
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_19 | R/W | 0h | Priority of interrupt 19 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_18 | R/W | 0h | Priority of interrupt 18 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_17 | R/W | 0h | Priority of interrupt 17 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_16 | R/W | 0h | Priority of interrupt 16 |
5-0 | RESERVED | R | 0h | Reserved |
IPR5 is shown in Table 2-83.
Return to the Summary Table.
Interrupt Priority Register 5
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_23 | R/W | 0h | Priority of interrupt 23 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_22 | R/W | 0h | Priority of interrupt 22 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_21 | R/W | 0h | Priority of interrupt 21 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_20 | R/W | 0h | Priority of interrupt 20 |
5-0 | RESERVED | R | 0h | Reserved |
IPR6 is shown in Table 2-84.
Return to the Summary Table.
Interrupt Priority Register 6
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_27 | R/W | 0h | Priority of interrupt 27 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_26 | R/W | 0h | Priority of interrupt 26 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_25 | R/W | 0h | Priority of interrupt 25 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_24 | R/W | 0h | Priority of interrupt 24 |
5-0 | RESERVED | R | 0h | Reserved |
IPR7 is shown in Table 2-85.
Return to the Summary Table.
Interrupt Priority Register 7
Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | IP_31 | R/W | 0h | Priority of interrupt 31 |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | IP_30 | R/W | 0h | Priority of interrupt 30 |
21-16 | RESERVED | R | 0h | Reserved |
15-14 | IP_29 | R/W | 0h | Priority of interrupt 29 |
13-8 | RESERVED | R | 0h | Reserved |
7-6 | IP_28 | R/W | 0h | Priority of interrupt 28 |
5-0 | RESERVED | R | 0h | Reserved |