SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 10-94 lists the memory-mapped registers for the LGPT2 registers. All register offset addresses not listed in Table 10-94 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Description Register. | Go |
4h | DESCEX | Description Extended | Go |
8h | STARTCFG | Start Configuration | Go |
Ch | CTL | Timer Control | Go |
10h | OUTCTL | Output Control | Go |
14h | CNTR | Counter | Go |
18h | PRECFG | Clock Prescaler Configuration | Go |
1Ch | PREEVENT | Prescaler Event | Go |
20h | CHFILT | Channel Input Filter | Go |
34h | QDECSTAT | Quadrature Decoder Status | Go |
3Ch | DMA | Direct Memory Accsess | Go |
40h | DMARW | Direct Memory Access | Go |
44h | ADCTRG | ADC Trigger | Go |
48h | IOCTL | IO Controller | Go |
68h | IMASK | Interrupt mask. | Go |
6Ch | RIS | Raw interrupt status. | Go |
70h | MIS | Masked interrupt status. | Go |
74h | ISET | Interrupt set register. | Go |
78h | ICLR | Interrupt clear register. | Go |
7Ch | IMSET | Interrupt mask set register. | Go |
80h | IMCLR | Interrupt mask clear register. | Go |
84h | EMU | Debug control | Go |
C0h | C0CFG | Channel 0 Configuration | Go |
C4h | C1CFG | Channel 1 Configuration | Go |
C8h | C2CFG | Channel 2 Configuration | Go |
FCh | PTGT | Pipeline Target | Go |
100h | PC0CC | Pipeline Channel 0 Capture Compare | Go |
104h | PC1CC | Pipeline Channel 1 Capture Compare | Go |
108h | PC2CC | Pipeline Channel 2 Capture Compare | Go |
13Ch | TGT | Target | Go |
140h | C0CC | Channel 0 Capture Compare | Go |
144h | C1CC | Channel 1 Capture Compare | Go |
148h | C2CC | Channel 2 Capture Compare | Go |
17Ch | PTGTNC | Pipeline Target No Clear | Go |
180h | PC0CCNC | Pipeline Channel 0 Capture Compare No Clear | Go |
184h | PC1CCNC | Pipeline Channel 1 Capture Compare No Clear | Go |
188h | PC2CCNC | Pipeline Channel 2 Capture Compare No Clear | Go |
1BCh | TGTNC | Target No Clear | Go |
1C0h | C0CCNC | Channel 0 Capture Compare No Clear | Go |
1C4h | C1CCNC | Channel 1 Capture Compare No Clear | Go |
1C8h | C2CCNC | Channel 2 Capture Compare No Clear | Go |
Complex bit access types are encoded to fit into small table cells. Table 10-95 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 10-96.
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Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | DE49h | Module identifier used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 1h | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
11-8 | INSTIDX | R | 0h | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number. |
7-4 | MAJREV | R | 1h | Major revision of IP. |
3-0 | MINREV | R | 0h | Minor revision of IP. |
DESCEX is shown in Table 10-97.
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Description Extended
This register describes the parameters of the LGPT.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19 | HIR | R | 0h | Has IR logic. |
18 | HDBF | R | 0h | Has deadband, fault, and park logic. |
17-14 | PREW | R | 8h | Prescale width. The prescaler can maximum be configured to 2PREW-1. |
13 | HQDEC | R | 1h | Has Quadrature Decoder. |
12 | HCIF | R | 1h | Has channel input filter. |
11-8 | CIFS | R | 8h | Channel input filter size. The prevailing state filter can maximum be configured to 2CIFS-1. |
7 | HDMA | R | 1h | Has uDMA output and logic. |
6 | HINT | R | 1h | Has interrupt output and logic. |
5-4 | CNTRW | R | 0h | Counter bit-width. The maximum counter value is equal to 2CNTRW-1. 0h = 16-bit counter. 1h = 24-bit counter. 2h = 32-bit counter. 3h = RESERVED |
3-0 | NCH | R | 3h | Number of channels. |
STARTCFG is shown in Table 10-98.
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Start Configuration
This register is only for when CTL.MODE is configured to one of the SYNC modes.
This register defines when this LGPT starts.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | LGPT0 | R/W | 0h | LGPT start |
CTL is shown in Table 10-99.
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Timer Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2RST | W | 0h | Channel 2 reset. 0h = No effect. 1h = Reset C2CC, PC2CC, and C2CFG. |
9 | C1RST | W | 0h | Channel 1 reset. 0h = No effect. 1h = Reset C1CC, PC1CC, and C1CFG. |
8 | C0RST | W | 0h | Channel 0 reset. 0h = No effect. 1h = Reset C0CC, PC0CC, and C0CFG. |
7-6 | RESERVED | R | 0h | Reserved |
5 | INTP | R/W | 0h | Interrupt Phase. This bit field controls when the RIS.TGT and RIS.ZERO interrupts are set. 0h = RIS.TGT and RIS.ZERO are set one system clock cycle after CNTR = TARGET/ZERO. 1h = RIS.TGT and RIS.ZERO are set one timer clock cycle after CNTR = TARGET/ZERO. |
4-3 | CMPDIR | R/W | 0h | Compare direction. This bit field controls the direction the counter must have in order to set the RIS.CnCC channel interrupts. This bitfield is only relevant if [CnCFG.CCACT] is configured to a compare action. 0h = Compare RIS fields are set on up count and down count. 1h = Compare RIS fields are only set on up count. 2h = Compare RIS fields are only set on down count. 3h = RESERVED |
2-0 | MODE | R/W | 0h | Timer mode control The CNTR restarts from 0 when MODE is written to UP_ONCE, UP_PER, UPDWN_PER, QDEC, SYNC_UP_ONCE, SYNC_UP_PER or SYNC_UPDWN_PER. When writing MODE all internally queued updates to the channels and TGT is cleared. When configuring the timer, MODE should be the last thing to configure. If changing timer configuration after MODE has been set is necessary, instructions, if any, given in the configuration registers should be followed. See for example C0CFG. 0h = Disable timer. Updates to counter, channels, and events stop. 1h = Count up once. The timer increments from 0 to target value, then stops and sets MODE to DIS. 2h = Count up periodically. The timer increments from 0 to target value, repeatedly. Period = (target value + 1) * timer clock period 3h = Count up and down periodically. The timer counts from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period 4h = The timer functions as a quadrature decoder. IOC input 0, IOC input 1 and IOC input 2 are used respectivly as PHA, PHB and IDX inputs. IDX can be turned off by setting C2CFG.EDGE = NONE. The timer clock frequency sets the sample rate of the QDEC logic. This frequency can be configured in PRECFG. 5h = Start counting up once synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_ONCE automatically. It then functions as a normal timer in CTL.MODE = UP_ONCE, incrementing from 0 to target value, then stops and sets MODE to DIS. 6h = Start counting up periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UP_PER automatically. It then operates as a normal timer in CTL.MODE = UP_PER, incrementing from 0 to target value, repeatedly. Period = (target value * 2) * timer clock period 7h = Start counting up and down periodically synchronous to another LGPT, selected within STARTCFG. The timer is started by setting CTL.MODE = UPDWN_PER automatically. It then operates as a normal timer in CTL.MODE = UPDWN_PER, counting from 0 to target value and back to 0, repeatedly. Period = (target value * 2) * timer clock period |
OUTCTL is shown in Table 10-100.
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Output Control
Set and clear individual outputs manually. Manual update of an output takes priority over automatic channel updates to the same output. It is not possible to set and clear an output at the same time, such requests will be neglected.
An output can be automatically cleared, set, toggled, or pulsed by each channel, listed in decreasing order of priority. The action with highest priority happens when multiple channels want to update an output at the same time.
All outputs are connected to the event fabric and the IO controller. The outputs going to the IO controller have an aditional complementary output, this output is the inverted IO output. Both the IO and the IO complementary outputs are passed through an IO Controller, see IOCTL.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | SETOUT2 | W | 0h | Set output 2. Write 1 to set output 2. |
4 | CLROUT2 | W | 0h | Clear output 2. Write 1 to clear output 2. |
3 | SETOUT1 | W | 0h | Set output 1. Write 1 to set output 1. |
2 | CLROUT1 | W | 0h | Clear output 1. Write 1 to clear output 1. |
1 | SETOUT0 | W | 0h | Set output 0. Write 1 to set output 0. |
0 | CLROUT0 | W | 0h | Clear output 0. Write 1 to clear output 0. |
CNTR is shown in Table 10-101.
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Counter
The counter of this timer. After CTL.MODE is set the counter updates at the rate specified in PRECFG.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Current counter value. If CTL.MODE = QDEC this can be used to set the initial counter value during QDEC. Writing to CNTR in other modes than QDEC is possible, but may result in unpredictable behavior. |
PRECFG is shown in Table 10-102.
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Clock Prescaler Configuration
This register is used to set the timer clock period. The prescaler is a counter which counts down from the value TICKDIV. When the prescaler counter reaches zero, CNTR is updated. The field TICKDIV effectively divides the prescaler tick source. The timer clock frequency can be calculated as TICKSRC/(TICKDIV+1).
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | TICKDIV | R/W | 0h | Tick division. TICKDIV determines the timer clock frequency for the counter, and timer output updates. The timer clock frequency is the clock selected by TICKSRC divided by (TICKDIV + 1). This inverse is the timer clock period. 0x00: Divide by 1. 0x01: Divide by 2. ... 0xFF: Divide by 256. |
7-2 | RESERVED | R | 0h | Reserved |
1-0 | TICKSRC | R/W | 0h | Prescaler tick source. TICKSRC determines the source which decrements the prescaler. 0h = Prescaler is updated at the system clock. 1h = Prescaler is updated at the rising edge of TICKEN. 2h = Prescaler is updated at the falling edge of TICKEN. 3h = Prescaler is updated at both edges of TICKEN. |
PREEVENT is shown in Table 10-103.
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Prescaler Event
This register is used to output a logic high signal before the zero crossing of the prescaler counter. The output is routed to the IOC.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | VAL | R/W | 0h | Sets the HIGH time of the prescaler event output. Event goes high when the prescaler counter equals VAL. Event goes low when prescaler counter is 0. Note: - Can be used to precharge or turn an external component on for a short time before sampling, like in QDEC. - If there is a requirement to create such events that have very short periods compared to timer clock period, use two timers. One timer acts as prescaler and event generator for another timer. |
CHFILT is shown in Table 10-104.
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Channel Input Filter
This register is used to configure the filter on the channel inputs. The configuration is for all inputs.
The filter is enabled when a channel is in capture mode.
The input to the filter is passed to the edge detection logic if LOAD + 1 consecutive input samples are equal. The filter functions as a down counter, counting down every input sample.
If two consecutive samples are unequal, the filter counter restarts from LOAD.
If the filter counter reaches zero, the input signal is valid and passed to the edge detection logic.
The channel filter should only be configured while the CTL.MODE = DIS. Configuring the filter while the timer is running can result in unexpected behavior.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | LOAD | R/W | 0h | The input of the channel filter is passed to the edge detection logic after LOAD + 1 consecutive equal samples. |
7-2 | RESERVED | R | 0h | Reserved |
1-0 | MODE | R/W | 0h | Channel filter mode 0h = Filter is bypassed. No Filter is used. 1h = Filter is clocked by system clock. 2h = Filter is clocked by PRECFG.TICKSRC. 3h = Filter is clocked by timer clock. |
QDECSTAT is shown in Table 10-105.
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Quadrature Decoder Status
This register can be used during QDEC mode to check the status of the quadrature decoder.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | DBLTRANS | R | 0h | Double transition 0h = Single or no transition on phase inputs. 1h = Double transition on phase inputs. |
0 | QDIR | R | 0h | Direction of count during QDEC mode. 0h = Up (PHA leads PHB) 1h = Down (PHB leads PHA) |
DMA is shown in Table 10-106.
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Direct Memory Accsess
This register is used to enable DMA requests from the timer and set the register addresses which the DMA will access (read/write).
Choose DMA request source by setting the REQ field. The setting of the corresponding interrupt in the RIS registers also sets the DMA request.
Upon a DMA request defined by REQ an internal address pointer is set to RWADDR*4. Every access to DMARW will increment the internal pointer by 4 such that the next DMA access will be to the next register.
The internal pointer will stop after RWCNTR increments. Further access will be ignored.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | RWCNTR | R/W | 0h | The read/write counter. RWCNTR+1 is the number of times the DMA can access (read/write) the DMARW register. For each DMA access to DMARW an internal counter is incremented, writing to the next address field. RWADDR + 4*RWCNTR is the final register address which can be accessed by the DMA. |
15 | RESERVED | R | 0h | Reserved |
14-8 | RWADDR | R/W | 0h | The base address which the DMA access when reading/writing DMARW. The base address is set by taking the 9 LSB of the physical address and divide by 4. For example, if you wanted the RWADDR to point to the PTGT register you should set RWADDR = 0x0FC/4. |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | REQ | R/W | 0h | 0h = Disabled 1h = Setting of RIS.TGT generates a DMA request. 2h = Setting of RIS.ZERO generates a DMA request. 3h = Setting of RIS.FAULT generates a DMA request. 4h = Setting of RIS.C0CC generates a DMA request. 5h = Setting of RIS.C1CC generates a DMA request. 6h = Setting of RIS.C2CC generates a DMA request. 7h = Setting of RIS.C3CC generates a DMA request. 8h = Setting of RIS.C4CC generates a DMA request. 9h = Setting of RIS.C5CC generates a DMA request. Ah = Setting of RIS.C6CC generates a DMA request. Bh = Setting of RIS.C7CC generates a DMA request. Ch = Setting of RIS.C8CC generates a DMA request. Dh = Setting of RIS.C9CC generates a DMA request. Eh = Setting of RIS.C10CC generates a DMA request. Fh = Setting of RIS.C11CC generates a DMA request. |
DMARW is shown in Table 10-107.
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Direct Memory Access
This register is used by the DMA to access (read/write) register inside this LGPT module.
Each access to this register will increment the internal DMA address counter. See DMA for description.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | DMA read write value. The value that is read/written from/to the registers. |
ADCTRG is shown in Table 10-108.
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ADC Trigger
This register is used to enable ADC trigger from the timer.
Choose ADC trigger source by setting the SRC field. The setting of the corresponding interrupt in the RIS registers also sets the ADC trigger.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | SRC | R/W | 0h | 0h = Disabled 1h = Setting of RIS.TGT generates an ADC trigger. 2h = Setting of RIS.ZERO generates an ADC trigger. 3h = Setting of RIS.FAULT generates an ADC trigger. 4h = Setting of RIS.C0CC generates an ADC trigger. 5h = Setting of RIS.C1CC generates an ADC trigger. 6h = Setting of RIS.C2CC generates an ADC trigger. 7h = Setting of RIS.C3CC generates an ADC trigger. 8h = Setting of RIS.C4CC generates an ADC trigger. 9h = Setting of RIS.C5CC generates an ADC trigger. Ah = Setting of RIS.C6CC generates an ADC trigger. Bh = Setting of RIS.C7CC generates an ADC trigger. Ch = Setting of RIS.C8CC generates an ADC trigger. Dh = Setting of RIS.C9CC generates an ADC trigger. Eh = Setting of RIS.C10CC generates an ADC trigger. Fh = Setting of RIS.C11CC generates an ADC trigger. |
IOCTL is shown in Table 10-109.
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IO Controller
This register overrides the IO outputs.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-10 | COUT2 | R/W | 0h | IO complementary output 2 control This bit field controls IO complementary output 2. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted. |
9-8 | OUT2 | R/W | 0h | IO output 2 control This bit field controls IO output 2. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted. |
7-6 | COUT1 | R/W | 0h | IO complementary output 1 control This bit field controls IO complementary output 1. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted. |
5-4 | OUT1 | R/W | 0h | IO output 1 control This bit field controls IO output 1. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted. |
3-2 | COUT0 | R/W | 0h | IO complementary output 0 control This bit field controls IO complementary output 0. 0h = Normal output. The IO complementary output is not changed. 1h = Driven low. The IO complementary output is driven low. 2h = Driven high. The IO complementary output is driven high. 3h = Inverted value. The IO complementary output is inverted. |
1-0 | OUT0 | R/W | 0h | IO output 0 control This bit field controls IO output 0. 0h = Normal output. The IO output is not changed. 1h = Driven low. The IO output is driven low. 2h = Driven high. The IO output is driven high. 3h = Inverted value. The IO output is inverted. |
IMASK is shown in Table 10-110.
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Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | R/W | 0h | Enable RIS.C2CC interrupt. 0h = Disable 1h = Enable |
9 | C1CC | R/W | 0h | Enable RIS.C1CC interrupt. 0h = Disable 1h = Enable |
8 | C0CC | R/W | 0h | Enable RIS.C0CC interrupt. 0h = Disable 1h = Enable |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | R/W | 0h | Enable RIS.FAULT interrupt. 0h = Disable 1h = Enable |
5 | IDX | R/W | 0h | Enable RIS.IDX interrupt. 0h = Disable 1h = Enable |
4 | DIRCHNG | R/W | 0h | Enable RIS.DIRCHNG interrupt. 0h = Disable 1h = Enable |
3 | CNTRCHNG | R/W | 0h | Enable RIS.CNTRCHNG interrupt. 0h = Disable 1h = Enable |
2 | DBLTRANS | R/W | 0h | Enable RIS.DBLTRANS interrupt. 0h = Disable 1h = Enable |
1 | ZERO | R/W | 0h | Enable RIS.ZERO interrupt. 0h = Disable 1h = Enable |
0 | TGT | R/W | 0h | Enable RIS.TGT interrupt. 0h = Disable 1h = Enable |
RIS is shown in Table 10-111.
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Raw interrupt status.
This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | R | 0h | Status of the C2CC interrupt. The interrupt is set when C2CC has capture or compare event. 0h = Cleared 1h = Set |
9 | C1CC | R | 0h | Status of the C1CC interrupt. The interrupt is set when C1CC has capture or compare event. 0h = Cleared 1h = Set |
8 | C0CC | R | 0h | Status of the C0CC interrupt. The interrupt is set when C0CC has capture or compare event. 0h = Cleared 1h = Set |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | R | 0h | Status of the FAULT interrupt. The interrupt is set immediately on active fault input. 0h = Cleared 1h = Set |
5 | IDX | R | 0h | Status of the IDX interrupt. The interrupt is set when IDX is active. 0h = Cleared 1h = Set |
4 | DIRCHNG | R | 0h | Status of the DIRCHNG interrupt. The interrupt is set when the direction of the counter changes. 0h = Cleared 1h = Set |
3 | CNTRCHNG | R | 0h | Status of the CNTRCHNG interrupt. The interrupt is set when the counter increments or decrements. 0h = Cleared 1h = Set |
2 | DBLTRANS | R | 0h | Status of the DBLTRANS interrupt. The interrupt is set when a double transition has happened during QDEC mode. 0h = Cleared 1h = Set |
1 | ZERO | R | 0h | Status of the ZERO interrupt. The interrupt is set when CNTR = 0. 0h = Cleared 1h = Set |
0 | TGT | R | 0h | Status of the TGT interrupt. The interrupt is set when CNTR = TGT. 0h = Cleared 1h = Set |
MIS is shown in Table 10-112.
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Masked interrupt status.
This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | R | 0h | Masked status of the RIS.C2CC interrupt. 0h = Cleared 1h = Set |
9 | C1CC | R | 0h | Masked status of the RIS.C1CC interrupt. 0h = Cleared 1h = Set |
8 | C0CC | R | 0h | Masked status of the RIS.C0CC interrupt. 0h = Cleared 1h = Set |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | R | 0h | Masked status of the RIS.FAULT interrupt. 0h = Cleared 1h = Set |
5 | IDX | R | 0h | Masked status of the RIS.IDX interrupt. 0h = Cleared 1h = Set |
4 | DIRCHNG | R | 0h | Masked status of the RIS.DIRCHNG interrupt. 0h = Cleared 1h = Set |
3 | CNTRCHNG | R | 0h | Masked status of the RIS.CNTRCHNG interrupt. 0h = Cleared 1h = Set |
2 | DBLTRANS | R | 0h | Masked status of the RIS.DBLTRANS interrupt. 0h = Cleared 1h = Set |
1 | ZERO | R | 0h | Masked status of the RIS.ZERO interrupt. 0h = Cleared 1h = Set |
0 | TGT | R | 0h | Masked status of the RIS.TGT interrupt. 0h = Cleared 1h = Set |
ISET is shown in Table 10-113.
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Interrupt set register.
This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | W | 0h | Set the RIS.C2CC interrupt. 0h = No effect 1h = Set |
9 | C1CC | W | 0h | Set the RIS.C1CC interrupt. 0h = No effect 1h = Set |
8 | C0CC | W | 0h | Set the RIS.C0CC interrupt. 0h = No effect 1h = Set |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | W | 0h | Set the RIS.FAULT interrupt. 0h = No effect 1h = Set |
5 | IDX | W | 0h | Set the RIS.IDX interrupt. 0h = No effect 1h = Set |
4 | DIRCHNG | W | 0h | Set the RIS.DIRCHNG interrupt. 0h = No effect 1h = Set |
3 | CNTRCHNG | W | 0h | Set the RIS.CNTRCHNG interrupt. 0h = No effect 1h = Set |
2 | DBLTRANS | W | 0h | Set the RIS.DBLTRANS interrupt. 0h = No effect 1h = Set |
1 | ZERO | W | 0h | Set the RIS.ZERO interrupt. 0h = No effect 1h = Set |
0 | TGT | W | 0h | Set the RIS.TGT interrupt. 0h = No effect 1h = Set |
ICLR is shown in Table 10-114.
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Interrupt clear register.
This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | W | 0h | Clear the RIS.C2CC interrupt. 0h = No effect 1h = Clear |
9 | C1CC | W | 0h | Clear the RIS.C1CC interrupt. 0h = No effect 1h = Clear |
8 | C0CC | W | 0h | Clear the RIS.C0CC interrupt. 0h = No effect 1h = Clear |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | W | 0h | Clear the RIS.FAULT interrupt. 0h = No effect 1h = Clear |
5 | IDX | W | 0h | Clear the RIS.IDX interrupt. 0h = No effect 1h = Clear |
4 | DIRCHNG | W | 0h | Clear the RIS.DIRCHNG interrupt. 0h = No effect 1h = Clear |
3 | CNTRCHNG | W | 0h | Clear the RIS.CNTRCHNG interrupt. 0h = No effect 1h = Clear |
2 | DBLTRANS | W | 0h | Clear the RIS.DBLTRANS interrupt. 0h = No effect 1h = Clear |
1 | ZERO | W | 0h | Clear the RIS.ZERO interrupt. 0h = No effect 1h = Clear |
0 | TGT | W | 0h | Clear the RIS.TGT interrupt. 0h = No effect 1h = Clear |
IMSET is shown in Table 10-115.
Return to the Summary Table.
Interrupt mask set register.
Writing a 1 to a bit in this register will set the corresponding IMASK bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | W | 0h | Set the MIS.C2CC mask. 0h = No effect 1h = Set |
9 | C1CC | W | 0h | Set the MIS.C1CC mask. 0h = No effect 1h = Set |
8 | C0CC | W | 0h | Set the MIS.C0CC mask. 0h = No effect 1h = Set |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | W | 0h | Set the MIS.FAULT mask. 0h = No effect 1h = Set |
5 | IDX | W | 0h | Set the MIS.IDX mask. 0h = No effect 1h = Set |
4 | DIRCHNG | W | 0h | Set the MIS.DIRCHNG mask. 0h = No effect 1h = Set |
3 | CNTRCHNG | W | 0h | Set the MIS.CNTRCHNG mask. 0h = No effect 1h = Set |
2 | DBLTRANS | W | 0h | Set the MIS.DBLTRANS mask. 0h = No effect 1h = Set |
1 | ZERO | W | 0h | Set the MIS.ZERO mask. 0h = No effect 1h = Set |
0 | TGT | W | 0h | Set the MIS.TGT mask. 0h = No effect 1h = Set |
IMCLR is shown in Table 10-116.
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Interrupt mask clear register.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | C2CC | W | 0h | Clear the MIS.C2CC mask. 0h = No effect 1h = Clear |
9 | C1CC | W | 0h | Clear the MIS.C1CC mask. 0h = No effect 1h = Clear |
8 | C0CC | W | 0h | Clear the MIS.C0CC mask. 0h = No effect 1h = Clear |
7 | RESERVED | R | 0h | Reserved |
6 | FAULT | W | 0h | Clear the MIS.FAULT mask. 0h = No effect 1h = Clear |
5 | IDX | W | 0h | Clear the MIS.IDX mask. 0h = No effect 1h = Clear |
4 | DIRCHNG | W | 0h | Clear the MIS.DIRCHNG mask. 0h = No effect 1h = Clear |
3 | CNTRCHNG | W | 0h | Clear the MIS.CNTRCHNG mask. 0h = No effect 1h = Clear |
2 | DBLTRANS | W | 0h | Clear the MIS.DBLTRANS mask. 0h = No effect 1h = Clear |
1 | ZERO | W | 0h | Clear the MIS.ZERO mask. 0h = No effect 1h = Clear |
0 | TGT | W | 0h | Clear the MIS.TGT mask. 0h = No effect 1h = Clear |
EMU is shown in Table 10-117.
Return to the Summary Table.
Debug control
This register can be used to freeze the timer when CPU halts when HALT is set to 1. When HALT is set to 0, or when the CPU releases debug halt, the filters and edge detection logic is flushed and the timer starts. For setting a predefined output value during a CPU debug halt, PARK, if the timer has this register, should be configured additionally. If this timer does not have the PARK register a predefined output value during CPU halt is not possible.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CTL | R/W | 0h | Halt control. Configure when the counter shall stop upon CPU halt. This bitfield only applies if HALT = 1. 0h = Immediate reaction. The counter stops immediately on debug halt. 1h = Zero condition. The counter stops when CNTR = 0. |
0 | HALT | R/W | 0h | Halt LGPT when CPU is halted in debug. 0h = Disable. 1h = Enable. |
C0CFG is shown in Table 10-118.
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Channel 0 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | OUT2 | R/W | 0h | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 2. 1h = Channel 0 controls output 2. |
9 | OUT1 | R/W | 0h | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 1. 1h = Channel 0 controls output 1. |
8 | OUT0 | R/W | 0h | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 0 does not control output 0. 1h = Channel 0 controls output 0. |
7 | RESERVED | R | 0h | Reserved |
6 | INPUT | R/W | 0h | Select channel input. 0h = Event fabric 1h = IO controller |
5-4 | EDGE | R/W | 0h | Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges. |
3-0 | CCACT | R/W | 0h | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C0CC. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure INPUT (optional). - Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when C0CC.VAL = CNTR.VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE. Set enabled outputs and RIS.C0CC when C0CC.VAL contains signal period and PC0CC.VAL contains signal pulse width. Notes: - Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when C0CC.VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period. - Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C0CC.VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When C0CC.VAL <= TGT.VAL: Duty cycle = 1 - ( C0CC.VAL / TGT.VAL ). When C0CC.VAL > TGT.VAL: Duty cycle = 0. Enabled outputs are set when C0CC.VAL = 0 and CNTR.VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When C0CC.VAL <= TGT.VAL: Duty cycle = C0CC.VAL / ( TGT.VAL + 1 ). When C0CC.VAL > TGT.VAL: Duty cycle = 1. Enabled outputs are cleared when C0CC.VAL = 0 and CNTR.VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when C0CC.VAL = CNTR.VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when C0CC.VAL = CNTR.VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when C0CC.VAL = CNTR.VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when C0CC.VAL = CNTR.VAL. The output is high for two timer clock periods. |
C1CFG is shown in Table 10-119.
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Channel 1 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | OUT2 | R/W | 0h | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 2. 1h = Channel 1 controls output 2. |
9 | OUT1 | R/W | 0h | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 1. 1h = Channel 1 controls output 1. |
8 | OUT0 | R/W | 0h | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 1 does not control output 0. 1h = Channel 1 controls output 0. |
7 | RESERVED | R | 0h | Reserved |
6 | INPUT | R/W | 0h | Select channel input. 0h = Event fabric 1h = IO controller |
5-4 | EDGE | R/W | 0h | Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges. |
3-0 | CCACT | R/W | 0h | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C1CC. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure INPUT (optional). - Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when C1CC.VAL = CNTR.VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE. Set enabled outputs and RIS.C1CC when C1CC.VAL contains signal period and PC1CC.VAL contains signal pulse width. Notes: - Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when C1CC.VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period. - Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C1CC.VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When C1CC.VAL <= TGT.VAL: Duty cycle = 1 - ( C1CC.VAL / TGT.VAL ). When C1CC.VAL > TGT.VAL: Duty cycle = 0. Enabled outputs are set when C1CC.VAL = 0 and CNTR.VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When C1CC.VAL <= TGT.VAL: Duty cycle = C1CC.VAL / ( TGT.VAL + 1 ). When C1CC.VAL > TGT.VAL: Duty cycle = 1. Enabled outputs are cleared when C1CC.VAL = 0 and CNTR.VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when C1CC.VAL = CNTR.VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when C1CC.VAL = CNTR.VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when C1CC.VAL = CNTR.VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when C1CC.VAL = CNTR.VAL. The output is high for two timer clock periods. |
C2CFG is shown in Table 10-120.
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Channel 2 Configuration
This register configures channel function and enables outputs.
Each channel has an edge-detection circuit. The the edge-detection circuit is:
- enabled while CCACT selects a capture function and CTL.MODE is different from DIS.
- flushed while CCACT selects a capture function and CTL.MODE is changed from DIS to another mode.
The flush action uses two system clock periods. It prevents capture events caused by expired signal values stored in the edge-detection circuit.
The channel input signal enters the edge-detection circuit. False capture events can occur when:
- the edge-detection circuit contains expired signal samples and the circuit is enabled without flush as described above.
- the CCACT field is reconfigured while CTL.MODE is different from DIS.
Primary use scenario is to select CCACT before starting the timer. Follow these steps to configure CCACT to a capture action while CTL.MODE is different from DIS:
- Set EDGE to NONE.
- Configure CCACT.
- Wait for three system clock periods before setting EDGE different from NONE.
These steps prevent capture events caused by expired signal values in edge-detection circuit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10 | OUT2 | R/W | 0h | Output 2 enable. When 0 < CCACT < 8, OUT2 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 2. 1h = Channel 2 controls output 2. |
9 | OUT1 | R/W | 0h | Output 1 enable. When 0 < CCACT < 8, OUT1 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 1. 1h = Channel 2 controls output 1. |
8 | OUT0 | R/W | 0h | Output 0 enable. When 0 < CCACT < 8, OUT0 becomes zero after a capture or compare event. 0h = Channel 2 does not control output 0. 1h = Channel 2 controls output 0. |
7 | RESERVED | R | 0h | Reserved |
6 | INPUT | R/W | 0h | Select channel input. 0h = Event fabric 1h = IO controller |
5-4 | EDGE | R/W | 0h | Determines the edge that triggers the channel input event. This happens post filter. 0h = Input is turned off. 1h = Input event is triggered at rising edge. 2h = Input event is triggered at falling edge. 3h = Input event is triggered at both edges. |
3-0 | CCACT | R/W | 0h | Capture-Compare action. Capture-Compare action defines 15 different channel functions that utilize capture, compare, and zero events. In every compare event the timer looks at the current value of CNTR. The corresponding output event will be set 1 timer period after CNTR = C2CC. 0h = Disable channel. 1h = Set on capture, and then disable channel. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL. - Disable channel. Primary use scenario is to select this function before starting the timer. Follow these steps to select this function while CTL.MODE is different from DIS: - Set CCACT to SET_ON_CAPT with no output enable. - Configure INPUT (optional). - Wait for three timer clock periods as defined in PRECFG before setting CCACT to SET_ON_CAPT_DIS. Output enable is optional. These steps prevent capture events caused by expired signal values in edge-detection circuit. 2h = Clear on zero, toggle on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0. 3h = Set on zero, toggle on compare, and then disable channel. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0. 4h = Clear on compare, and then disable channel. Channel function sequence: - Clear enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. 5h = Set on compare, and then disable channel. Channel function sequence: - Set enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. 6h = Toggle on compare, and then disable channel. Channel function sequence: - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. 7h = Pulse on compare, and then disable channel. Channel function sequence: - Pulse enabled outputs when C2CC.VAL = CNTR.VAL. - Disable channel. The output is high for two timer clock periods. 8h = Period and pulse width measurement. Continuously capture period and pulse width of the signal selected by INPUT relative to the signal edge given by EDGE. Set enabled outputs and RIS.C2CC when C2CC.VAL contains signal period and PC2CC.VAL contains signal pulse width. Notes: - Make sure to configure INPUT and CCACT when CTL.MODE equals DIS, then set CTL.MODE to UP_ONCE or UP_PER. - The counter restarts in the selected timer mode when C2CC.VAL contains the signal period. - If more than one channel uses this function, the channels will perform this function one at a time. The channel with lowest number has priority and performs the function first. Next measurement starts when current measurement completes successfully or times out. A timeout occurs when counter equals target. - To observe a timeout event the RIS.TGT interrupt can be used, or another channel can be configured to SET_ON_CMP with compare value equal TGT. Signal property requirements: - Signal Period >= 2 * ( 1 + PRECFG.TICKDIV ) * timer clock period. - Signal Period <= MAX(CNTR) * (1 + PRECFG.TICKDIV ) * timer clock period. - Signal low and high phase >= (1 + PRECFG.TICKDIV ) * timer clock period. 9h = Set on capture repeatedly. Channel function sequence: - Set enabled outputs on capture event and copy CNTR.VAL to C2CC.VAL. Ah = Clear on zero, toggle on compare repeatedly. Channel function sequence: - Clear enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. Set CTL.MODE to UPDWN_PER for center-aligned PWM generation. Duty cycle is given by: When C2CC.VAL <= TGT.VAL: Duty cycle = 1 - ( C2CC.VAL / TGT.VAL ). When C2CC.VAL > TGT.VAL: Duty cycle = 0. Enabled outputs are set when C2CC.VAL = 0 and CNTR.VAL = 0. Bh = Set on zero, toggle on compare repeatedly. Channel function sequence: - Set enabled outputs when CNTR.VAL = 0. - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. Set CTL.MODE to UP_PER for edge-aligned PWM generation. Duty cycle is given by: When C2CC.VAL <= TGT.VAL: Duty cycle = C2CC.VAL / ( TGT.VAL + 1 ). When C2CC.VAL > TGT.VAL: Duty cycle = 1. Enabled outputs are cleared when C2CC.VAL = 0 and CNTR.VAL = 0. Ch = Clear on compare repeatedly. Channel function sequence: - Clear enabled outputs when C2CC.VAL = CNTR.VAL. Dh = Set on compare repeatedly. Channel function sequence: - Set enabled outputs when C2CC.VAL = CNTR.VAL. Eh = Toggle on compare repeatedly. Channel function sequence: - Toggle enabled outputs when C2CC.VAL = CNTR.VAL. Fh = Pulse on compare repeatedly. Channel function sequence: - Pulse enabled outputs when C2CC.VAL = CNTR.VAL. The output is high for two timer clock periods. |
PTGT is shown in Table 10-121.
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Pipeline Target
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.
If CTL.MODE != QDEC.
Target value for next counter period.
The timer will copy PTGT.VAL to TGT.VAL on the upcoming CNTR zero crossing only if PTGT.VAL has been written. The copy does not happen when restarting the timer.
This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM.
If CTL.MODE = QDEC
The CNTR value is updated with VALUE on IDX if the counter is counting down. If the counter is counting up, CNTR is loaded with zero on IDX.
In this mode the VALUE is not loaded into TGT on zero crossing.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | The pipleline target value. |
PC0CC is shown in Table 10-122.
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Pipeline Channel 0 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C0CC interrupt. Compare mode: An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE. |
PC1CC is shown in Table 10-123.
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Pipeline Channel 1 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C1CC interrupt. Compare mode: An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE. |
PC2CC is shown in Table 10-124.
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Pipeline Channel 2 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will clear the RIS.C2CC interrupt. Compare mode: An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE. |
TGT is shown in Table 10-125.
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Target
User defined counter target.
A read or write to this register will clear the RIS.ZERO and RIS.TGT interrupt.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | FFFFh | User defined counter target value. |
C0CC is shown in Table 10-126.
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Channel 0 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C0CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value. |
C1CC is shown in Table 10-127.
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Channel 1 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C1CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value. |
C2CC is shown in Table 10-128.
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Channel 2 Capture Compare
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will clear the RIS.C2CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value. |
PTGTNC is shown in Table 10-129.
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Pipeline Target No Clear
Use this register to read or write to PTGT without clearing the RIS.ZERO and RIS.TGT interrupt.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | A read or write to this register will not clear the RIS.TGT interrupt. If CTL.MODE != QDEC. Target value for next counter period. The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not happen when restarting the timer. This is useful to avoid period jitter in PWM applications with time-varying period, sometimes referenced as phase corrected PWM. If CTL.MODE = QDEC. The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when CNTR.VAL becomes 0. |
PC0CCNC is shown in Table 10-130.
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Pipeline Channel 0 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C0CC interrupt. Compare mode: An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C0CFG.EDGE. |
PC1CCNC is shown in Table 10-131.
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Pipeline Channel 1 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C1CC interrupt. Compare mode: An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C1CFG.EDGE. |
PC2CCNC is shown in Table 10-132.
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Pipeline Channel 2 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Pipeline Capture Compare value. User defined pipeline compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C2CC interrupt. Compare mode: An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is zero and CTL.MODE is different from DIS. This is useful for PWM generation and prevents jitter on the edges of the generated signal. Capture mode: When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of the low or high phase of the selected signal. This is specified by C2CFG.EDGE. |
TGTNC is shown in Table 10-133.
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Target No Clear
Use this register to read or write to TGT without clearing the RIS.ZERO and RIS.TGT interrupt.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | FFFFh | User defined counter target value. |
C0CCNC is shown in Table 10-134.
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Channel 0 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C0CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C0CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C0CFG.CCACT determines if VAL is a signal period or a regular capture value. |
C1CCNC is shown in Table 10-135.
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Channel 1 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C1CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C1CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C1CFG.CCACT determines if VAL is a signal period or a regular capture value. |
C2CCNC is shown in Table 10-136.
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Channel 2 Capture Compare No Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Capture Compare value. User defined compare value or channel-updated capture value. A read or write to this register will not clear the RIS.C2CC interrupt. Compare mode: VAL is compared against CNTR.VAL and an event is generated as specified by C2CFG.CCACT when these are equal. Capture mode: The current counter value is stored in VAL when a capture event occurs. C2CFG.CCACT determines if VAL is a signal period or a regular capture value. |