SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 2-21 lists the memory-mapped registers for the CPU_ROM_TABLE registers. All register offset addresses not listed in Table 2-21 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | EntrySCS | ROM Table Entry | Go |
4h | EntryDWT | ROM Table Entry | Go |
8h | EntryBPU | ROM Table Entry | Go |
Ch | EntryEnd | ROM Table Entry | Go |
FCCh | MEMTYPE | MEMTYPE Register | Go |
FD0h | PIDR4 | Peripheral ID Register 4 | Go |
FD4h | PIDR5 | Peripheral ID Register 5 | Go |
FD8h | PIDR6 | Peripheral ID Register 6 | Go |
FDCh | PIDR7 | Peripheral ID Register 7 | Go |
FE0h | PIDR0 | Peripheral ID Register 0 | Go |
FE4h | PIDR1 | Peripheral ID Register 1 | Go |
FE8h | PIDR2 | Peripheral ID Register 2 | Go |
FECh | PIDR3 | Peripheral ID Register 3 | Go |
FF0h | CIDR0 | Component ID Register 0 | Go |
FF4h | CIDR1 | Component ID Register 1 | Go |
FF8h | CIDR2 | Component ID Register 2 | Go |
FFCh | CIDR3 | Component ID Register 3 | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-22 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Reset or Default Value | ||
-n | Value after reset or the default value |
EntrySCS is shown in Table 2-23.
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ROM Table Entry
Points to the System Control Space (SCS) at 0xE000E000. This includes core debug control registers.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | AddressOffset | R | 000FFF0Fh | Base address of the highest 4KB block for the component, relative to the ROM address. |
11-2 | RESERVED | R | 0h | Reserved |
1 | Format | R | 1h | Base address of the highest 4KB block for the component, relative to the ROM address. |
0 | EntryPresent | R | 1h | This bit indicates whether an entry is present at this location in the ROM table. 0x0:Rom table entry is not present and must be skipped. 0x1:Rom table entry is present. |
EntryDWT is shown in Table 2-24.
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ROM Table Entry
Points to the DW unit at 0xE0001000.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | AddressOffset | R | 000FFF02h | Base address of the highest 4KB block for the component, relative to the ROM address. |
11-2 | RESERVED | R | 0h | Reserved |
1 | Format | R | 1h | Base address of the highest 4KB block for the component, relative to the ROM address. |
0 | EntryPresent | R | 1h | This bit indicates whether an entry is present at this location in the ROM table. 0x0:Rom table entry is not present and must be skipped. 0x1:Rom table entry is present. |
EntryBPU is shown in Table 2-25.
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ROM Table Entry
Points to the BPU at 0xE0002000.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | AddressOffset | R | 000FFF03h | Base address of the highest 4KB block for the component, relative to the ROM address. |
11-2 | RESERVED | R | 0h | Reserved |
1 | Format | R | 1h | Base address of the highest 4KB block for the component, relative to the ROM address. |
0 | EntryPresent | R | 0h | This bit indicates whether an entry is present at this location in the ROM table. 0x0:Rom table entry is not present and must be skipped. 0x1:Rom table entry is present. |
EntryEnd is shown in Table 2-26.
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ROM Table Entry
Marks of end of table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | END | R | 0h | Blank ROM Table entry indicating the end of the ROM Table content. |
MEMTYPE is shown in Table 2-27.
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MEMTYPE Register
Identifies the type of memory present on the bus that connects the DAP to the ROM Table.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SYSMEM | R | 1h | System memory present. Indicates whether system memory is present on the bus that connects to the ROM table. 0x0:System memory not present on bus. this is a dedicated debug bus. 0x1:System memory is present on bus. |
PIDR4 is shown in Table 2-28.
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Peripheral ID Register 4
Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | SIZE | R | 0h | This is a 4-bit value that indicates the total contiguous size of the memory window used by this component in powers of 2 from the standard 4KB. If a component only requires the standard 4KB then this should read as 0x0, 4KB only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. |
3-0 | DES_2 | R | 4h | Number of JEDEC continuation codes. Indicates the designer of the component (along with the identity code) |
PIDR5 is shown in Table 2-29.
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Peripheral ID Register 5
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR6 is shown in Table 2-30.
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Peripheral ID Register 6
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR7 is shown in Table 2-31.
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Peripheral ID Register 7
Reserved
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
PIDR0 is shown in Table 2-32.
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Peripheral ID Register 0
Part of the set of Peripheral Identification registers. Contains part of the designer specific part number.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PART_0 | R | C0h | Bits [7:0] of the component's part number. This is selected by the designer of the component. |
PIDR1 is shown in Table 2-33.
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Peripheral ID Register 1
Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | DES_0 | R | Bh | Bits [3:0] of the JEDEC identity code indicating the designer of the component (along with the continuation code) |
3-0 | PART_1 | R | 4h | Bits [11:8] of the component's part number. This is selected by the designer of the component. |
PIDR2 is shown in Table 2-34.
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Peripheral ID Register 2
Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | REVISION | R | 0h | The Revision field is an incremental value starting at 0x0 for the first design of this component. This only increases by 1 for both major and minor revisions and is simply used as a look-up to establish the exact major/minor revision. |
3 | JEDEC | R | 1h | Always set. Indicates that a JEDEC assigned value is used |
2-0 | DES_1 | R | 3h | Bits [6:4] of the JEDEC identity code indicating the designer of the component (along with the continuation code) |
PIDR3 is shown in Table 2-35.
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Peripheral ID Register 3
Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | REVAND | R | 0h | This field indicates minor errata fixes specific to this design, for example metal fixes after implementation. In most cases this field is zero. It is recommended that component designers ensure this field can be changed by a metal fix if required, for example by driving it from registers that reset to zero. |
3-0 | CMOD | R | 0h | Where the component is reusable IP, this value indicates if the customer has modified the behavior of the component. In most cases this field is zero. |
CIDR0 is shown in Table 2-36.
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Component ID Register 0
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_0 | R | Dh | Contains bits [7:0] of the component identification |
CIDR1 is shown in Table 2-37.
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Component ID Register 1
A component identification register, that indicates that the identification registers are present. This register also indicates the component class.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-4 | CLASS | R | 1h | Class of the component. For example, ROM table, CoreSight component and so on. Constitutes bits [15:12] of the component identification. |
3-0 | PRMBL_1 | R | 0h | Contains bits [11:8] of the component identification |
CIDR2 is shown in Table 2-38.
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Component ID Register 2
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_2 | R | 5h | Contains bits [23:16] of the component identification |
CIDR3 is shown in Table 2-39.
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Component ID Register 3
A component identification register, that indicates that the identification registers are present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | PRMBL_3 | R | B1h | Contains bits [31:24] of the component identification |