SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 7-19 lists the memory-mapped registers for the FLASH registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
28h | IMASK | Interrupt Mask Register | Go |
30h | RIS | Raw Interrupt Status Register | Go |
38h | MIS | Masked Interrupt Status Register | Go |
40h | ISET | Interrupt Set Register | Go |
48h | ICLR | Interrupt Clear Register | Go |
FCh | DESC | Hardware Version Description Register | Go |
100h | CMDEXEC | Command Execute Register | Go |
104h | CMDTYPE | Command Type Register | Go |
108h | CMDCTL | Command Control Register | Go |
120h | CMDADDR | Command Address Register | Go |
124h | CMDBYTEN | Command Program Byte Enable Register | Go |
130h | CMDDATA0 | Command Data Register 0 | Go |
134h | CMDDATA1 | Command Data Register 1 | Go |
138h | CMDDATA2 | Command Data Register 2 | Go |
13Ch | CMDDATA3 | Command Data Register Bits 127:96 | Go |
1D0h | CMDWEPROTA | Command Write Erase Protect A Register | Go |
1D4h | CMDWEPROTB | Command Write Erase Protect B Register | Go |
210h | CMDWEPROTNM | Command Write Erase Protect Non-Main Register | Go |
214h | CMDWEPROTTR | Command Write Erase Protect Trim Register | Go |
218h | CMDWEPROTEN | Command Write Erase Protect Engr Register | Go |
3B0h | CFGCMD | Command Configuration Register | Go |
3B4h | CFGPCNT | Pulse Counter Configuration Register | Go |
3D0h | STATCMD | Command Status Register | Go |
3D4h | STATADDR | Address Status Register | Go |
3D8h | STATPCNT | Pulse Count Status Register | Go |
3DCh | STATMODE | Mode Status Register | Go |
3F0h | GBLINFO0 | Global Information Register 0 | Go |
3F4h | GBLINFO1 | Global Information Register 1 | Go |
3F8h | GBLINFO2 | Global Information Register 2 | Go |
400h | BANK0INFO0 | Bank Information Register 0 for Bank 0 | Go |
404h | BANK0INFO1 | Bank Information Register 1 for Bank 0 | Go |
Complex bit access types are encoded to fit into small table cells. Table 7-20 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
IMASK is shown in Table 7-21.
Return to the Summary Table.
Interrupt Mask Register:
The IMASK register holds the current interrupt mask settings. Masked interrupts
are read in the MIS register. PSD compliant register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | DONE | R/W | 0h | Interrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register 0h = Interrupt is masked out 1h = Interrupt will request an interrupt service routine and corresponding bit in IPSTANDARD.MIS will be set |
RIS is shown in Table 7-22.
Return to the Summary Table.
Raw Interrupt Status Register:
The RIS register reflects all pending interrupts, regardless of masking.
The RIS register allows the user to implement a poll scheme. A flag set in this
register can be cleared by writing a 1 to the ICLR register bit even if the
corresponding IMASK bit is not enabled. A flag can be set by software by writing
a 1 to the ISET register. Reading the IIDX register will also clear the
corresponding bit in RIS. PSD compliant register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | DONE | R | 0h | Flash wrapper operation completed. This interrupt bit is set by firmware or the corresponding bit in the ISET register. It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority. 0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Table 7-23.
Return to the Summary Table.
Masked Interrupt Status Register:
The MIS register is a bit-wise AND of the contents of the IMASK and RIS
registers. This is kept mainly for ARM compatibility, and has limited use since
the highest priority interrupt index is returned through the IIDX register.
PSD
compliant register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | DONE | R | 0h | Flash wrapper operation completed. This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits. 0h = Masked interrupt did not occur 1h = Masked interrupt occurred |
ISET is shown in Table 7-24.
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Interrupt Set Register:
The ISET register allows software to write a 1 to set corresponding interrupt.
Safety:
This meets a safety requirement to allow software diagnostics to trigger
interrupts.
PSD compliant register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | Reserved |
0 | DONE | W | 0h | 0: No effect 1: Set the DONE interrupt in the RIS register 0h = Writing a 0 has no effect 1h = Set IPSTANDARD.RIS bit |
ICLR is shown in Table 7-25.
Return to the Summary Table.
Interrupt Clear Register.
The ICLR register allows allows software to write a 1 to clear corresponding
interrupt.
PSD compliant register.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | 0h | Reserved |
0 | DONE | W | 0h | 0: No effect 1: Clear the DONE interrupt in the RIS register 0h = Writing a 0 has no effect 1h = Clear IPSTANDARD.RIS bit |
DESC is shown in Table 7-26.
Return to the Summary Table.
Hardware Version Description Register:
This register identifies the flash wrapper hardware version and feature set used.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | B40h | Module ID
0h = Smallest value FFFFh = Highest possible value |
15-12 | FEATUREVER | R | 1h | Feature set
0h = Minimum Value Fh = Maximum Value |
11-8 | INSTNUM | R | 0h | Instance number
0h = Smallest value Fh = Highest possible value |
7-4 | MAJREV | R | 1h | Major Revision
0h = Smallest value Fh = Highest possible value |
3-0 | MINREV | R | 0h | Minor Revision
0h = Smallest value Fh = Highest possible value |
CMDEXEC is shown in Table 7-27.
Return to the Summary Table.
Command Execute Register:
Initiates execution of the command specified in the CMDTYPE register.
This register is blocked for writes after being written to 1 and prior to
STATCMD.DONE being set by the flash wrapper hardware.
flash wrapper hardware clears this register after the processing of the command
has completed.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | VAL | R/W | 0h | Command Execute value Initiates execution of the command specified in the CMDTYPE register. 0h = Command will not execute or is not executing in flash wrapper 1h = Command will execute or is executing in flash wrapper |
CMDTYPE is shown in Table 7-28.
Return to the Summary Table.
Command Type Register
This register specifies the type of command to be executed by the flash wrapper
hardware.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | 0h | Reserved |
6-4 | SIZE | R/W | 0h | Command size
0h = Operate on 1 flash word 1h = Operate on 2 flash words 2h = Operate on 4 flash words 3h = Operate on 8 flash words 4h = Operate on a flash sector 5h = Operate on an entire flash bank |
3 | RESERVED | R/W | 0h | Reserved |
2-0 | COMMAND | R/W | 0h | Command type
0h = No Operation 1h = Program 2h = Erase 4h = Mode Change - Perform a mode change only, no other operation. 5h = Clear Status - Clear status bits in FW_SMSTAT only. 6h = Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD |
CMDCTL is shown in Table 7-29.
Return to the Summary Table.
Command Control Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R/W | 0h | Reserved |
21 | DATAVEREN | R/W | 0h | Enable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without executing the program. 0h = Disable 1h = Enable |
20 | SSERASEDIS | R/W | 0h | Disable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired. 0h = Enable 1h = Disable |
19-17 | RESERVED | R | 0h | Reserved |
16 | ADDRXLATEOVR | R/W | 0h | Override hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID. 0h = Do not override 1h = Override |
15-14 | RESERVED | R | 0h | Reserved |
13 | RESERVED | R/W | 0h | Reserved |
12-9 | REGIONSEL | R/W | 0h | Bank Region A specific region ID can be written to this field to indicate to which region an operation is to be applied if CMDCTL.ADDRXLATEOVR is set. 1h = Main Region 2h = Non-Main Region 4h = Trim Region 8h = Engr Region |
8-4 | RESERVED | R | 0h | Reserved |
3-0 | MODESEL | R/W | 0h | Mode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly through the NW hardware. 0h = Read Mode 2h = Read Margin 0 Mode 4h = Read Margin 1 Mode 6h = Read Margin 0B Mode 7h = Read Margin 1B Mode 9h = Program Verify Mode Ah = Program Single Word Bh = Erase Verify Mode Ch = Erase Sector Eh = Program Multiple Word Fh = Erase Bank |
CMDADDR is shown in Table 7-30.
Return to the Summary Table.
Command Address Register:
This register forms the target address of a command. The use cases are as
follows:
1) For single-word program, this address indicates the flash bank word to be
programmed.
2) For multi-word program, this address indicates the first flash bank address
for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
Note the address written to this register will be submitted for translation to the
flash wrapper address translation interface, and the translated address
will be used to access the bank. However, if the
CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will
be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Address value
0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDBYTEN is shown in Table 7-31.
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Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to
be programmed, a 1 must be written to the corresponding bit in this register.
Normally, all bits are written to 1, allowing program of full flash words.
However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit
or 64-bit portions of a flash word.
During verify, data bytes read from the flash will not be checked if the
corresponding CMDBYTEN bit is 0.
ECC data bytes are protected by the 1-2 MSB bits in this register, depending on
the presence of ECC and the flash word data width.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is written to all 0 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | Reserved |
17-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | Command Byte Enable value. A 1-bit per flash word byte value is placed in this register. 0h = Minimum value of VAL 0003FFFFh = Maximum value of VAL |
CMDDATA0 is shown in Table 7-32.
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Command Data Register 0
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDDATA1 is shown in Table 7-33.
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Command Data Register 1
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to CMDSTAT.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDDATA2 is shown in Table 7-34.
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Command Data Register 2
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDDATA3 is shown in Table 7-35.
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Command Data Register 3
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | A 32-bit data value is placed in this field.
0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDWEPROTA is shown in Table 7-36.
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Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from
program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32
sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | FFFFFFFFh | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase. 0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDWEPROTB is shown in Table 7-37.
Return to the Summary Table.
Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present,
the first 32 sectors are protected via the CMDWEPROTA register. Thus, the
protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first
32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only
bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of
bit 4 and above would begin at sector 32. Bits 3:0
of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has
no effect, so the bits in CMDWEPROTB will protect these banks starting
from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | 0h | Reserved |
27-0 | VAL | R/W | 0FFFFFFFh | Each bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register. 0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDWEPROTNM is shown in Table 7-38.
Return to the Summary Table.
Command WriteErase Protect Non-Main
Register
This register allows non-main region region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 1h | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase. 0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDWEPROTTR is shown in Table 7-39.
Return to the Summary Table.
Command WriteErase Protect Trim
Register
This register allows trim region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 1h | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CMDWEPROTEN is shown in Table 7-40.
Return to the Summary Table.
Command WriteErase Protect Engr
Register
This register allows engr region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 1h | Each bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase. 0h = Minimum value of VAL FFFFFFFFh = Maximum value of VAL |
CFGCMD is shown in Table 7-41.
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Command Configuration Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R/W | 0h | Reserved |
6-4 | RESERVED | R | 0h | Reserved |
3-0 | WAITSTATE | R/W | 2h | Wait State setting for verify reads
0h = Minimum value Fh = Maximum value |
CFGPCNT is shown in Table 7-42.
Return to the Summary Table.
Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for
program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-17 | RESERVED | R/W | 0h | Reserved |
16 | RESERVED | R | 0h | Reserved |
15-12 | RESERVED | R/W | 0h | Reserved |
11-4 | MAXPCNTVAL | R/W | 0h | Override maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}. 0h = Minimum value FFh = Maximum value |
3-1 | RESERVED | R/W | 0h | Reserved |
0 | MAXPCNTOVR | R/W | 0h | Override hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used. 0h = Use hard-wired (default) value for maximum pulse count 1h = Use value from MAXPCNTVAL field as maximum puse count |
STATCMD is shown in Table 7-43.
Return to the Summary Table.
Command Status Register
This register contains status regarding completion and errors of command
execution.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | 0h | Reserved |
12 | FAILMISC | R | 0h | Command failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit. 0h = No Fail 1h = Fail |
11-9 | RESERVED | R | 0h | Reserved |
8 | FAILINVDATA | R | 0h | Program command failed because an attempt was made to program a stored 0 value to a 1. 0h = No Fail 1h = Fail |
7 | FAILMODE | R | 0h | Command failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode. 0h = No Fail 1h = Fail |
6 | FAILILLADDR | R | 0h | Command failed due to the use of an illegal address
0h = No Fail 1h = Fail |
5 | FAILVERIFY | R | 0h | Command failed due to verify error
0h = No Fail 1h = Fail |
4 | FAILWEPROT | R | 0h | Command failed due to Write/Erase Protect Sector Violation
0h = No Fail 1h = Fail |
3 | RESERVED | R | 0h | Reserved |
2 | CMDINPROGRESS | R | 0h | Command In Progress
0h = Complete 1h = In Progress |
1 | CMDPASS | R | 0h | Command Pass - valid when CMD_DONE field is 1
0h = Fail 1h = Pass |
0 | CMDDONE | R | 0h | Command Done
0h = Not Done 1h = Done |
STATADDR is shown in Table 7-44.
Return to the Summary Table.
Current Address Counter Value
Read only register giving read access to the state machine current address.
A bank id, region id and address are stored in this register and are incremented as
necessary during execution of a command.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R | 0h | Reserved |
25-21 | BANKID | R | 1h | Current Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank. 1h = Bank 0 2h = Bank 1 4h = Bank 2 8h = Bank 3 10h = Bank 4 |
20-16 | REGIONID | R | 1h | Current Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating. 1h = Main Region 2h = Non-Main Region 4h = Trim Region 8h = Engr Region |
15-0 | BANKADDR | R | 0h | Current Bank Address A bank offset address is stored in this register. 0h = Minimum value FFFFh = Maximum value |
STATPCNT is shown in Table 7-45.
Return to the Summary Table.
Current Pulse Count Register:
Read only register giving read access to the state machine current pulse count
value for program/erase operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-0 | PULSECNT | R | 0h | Current Pulse Counter Value
0h = Minimum value FFFh = Maximum value |
STATMODE is shown in Table 7-46.
Return to the Summary Table.
Mode Status Register
Indicates one or more banks which not in READ mode, and it indicates the mode
which the bank(s) are in.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17 | BANK1TRDY | R | 0h | Bank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed. 0h = Not ready 1h = Ready |
16 | BANK2TRDY | R | 0h | Bank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s). 0h = Not ready 1h = Ready |
15-12 | RESERVED | R | 0h | Reserved |
11-8 | BANKMODE | R | 0h | Indicates mode of bank(s) that are not in READ mode
0h = Read Mode 2h = Read Margin 0 Mode 4h = Read Margin 1 Mode 6h = Read Margin 0B Mode 7h = Read Margin 1B Mode 9h = Program Verify Mode Ah = Program Single Word Bh = Erase Verify Mode Ch = Erase Sector Eh = Program Multiple Word Fh = Erase Bank |
7-5 | RESERVED | R | 0h | Reserved |
4-1 | RESERVED | R | 0h | Reserved |
0 | BANKNOTINRD | R | 0h | Bank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank. 1h = Bank 0 2h = Bank 1 4h = Bank 2 8h = Bank 3 10h = Bank 4 |
GBLINFO0 is shown in Table 7-47.
Return to the Summary Table.
Global Info 0 Register
Read only register detailing information about sector size and number of banks
present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | NUMBANKS | R | 1h | Number of banks instantiated Minimum: 1 Maximum: 5 1h = Minimum value 5h = Maximum value |
15-0 | SECTORSIZE | R | 800h | Sector size in bytes
400h = Sector size is ONEKB 800h = Sector size is TWOKB |
GBLINFO1 is shown in Table 7-48.
Return to the Summary Table.
Global Info 1 Register
Read only register detailing information about data, ecc and redundant data
widths in bits.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | REDWIDTH | R | 4h | Redundant data width in bits
0h = Redundant data width is 0. Redundancy/Repair not present. 2h = Redundant data width is 2 bits 4h = Redundant data width is 4 bits |
15-13 | RESERVED | R | 0h | Reserved |
12-8 | ECCWIDTH | R | 0h | ECC data width in bits
0h = ECC data width is 0. ECC not used. 8h = ECC data width is 8 bits 10h = ECC data width is 16 bits |
7-0 | DATAWIDTH | R | 80h | Data width in bits
40h = Data width is 64 bits 80h = Data width is 128 bits |
GBLINFO2 is shown in Table 7-49.
Return to the Summary Table.
Global Info 2 Register
Read only register detailing information about the number of data registers
present.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | DATAREGISTERS | R | 1h | Number of data registers present.
1h = Minimum value of DATAREGISTERS 8h = Maximum value of DATAREGISTERS |
BANK0INFO0 is shown in Table 7-50.
Return to the Summary Table.
Bank Info 0 Register for bank 0.
Read only register detailing information about Main region size in the bank.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-0 | MAINSIZE | R | 100h | Main region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512) 8h = Minimum value of MAINSIZE 200h = Maximum value of MAINSIZE |
BANK0INFO1 is shown in Table 7-51.
Return to the Summary Table.
Bank Info1 Register for bank 0.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-16 | ENGRSIZE | R | 1h | Engr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0h = Minimum value of ENGRSIZE 20h = Maximum value of ENGRSIZE |
15-8 | TRIMSIZE | R | 1h | Trim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0h = Minimum value of TRIMSIZE 20h = Maximum value of TRIMSIZE |
7-0 | NONMAINSIZE | R | 1h | Non-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16) 0h = Minimum value of NONMAINSIZE 20h = Maximum value of NONMAINSIZE |