SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

16.4 AES Registers

Table 16-1 lists the memory-mapped registers for the AES registers. All register offset addresses not listed in Table 16-1 should be considered as reserved locations and the register contents should not be modified.

Table 16-1 AES Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Go
10hTRGTriggerGo
14hABORTAbortGo
18hCLRClearGo
1ChSTAStatusGo
20hDMADirect Memory AccessGo
24hDMACHADMA Channel A data transferGo
28hDMACHBDMA Channel B data transferGo
2ChAUTOCFGAutomatic ConfigurationGo
50hKEY0Key Word 0Go
54hKEY1Key Word 1Go
58hKEY2Key Word 2Go
5ChKEY3Key Word 3Go
70hTXT0Text Word 0Go
74hTXT1Text Word 1Go
78hTXT2Text Word 2Go
7ChTXT3Text Word 3Go
80hTXTX0Text Word 0 XORGo
84hTXTX1Text Word 1 XORGo
88hTXTX2Text Word 2 XORGo
8ChTXTX3Text Word 3 XORGo
90hBUF0Buffer Word 0Go
94hBUF1Buffer Word 1Go
98hBUF2Buffer Word 2Go
9ChBUF3Buffer Word 3Go
A0hTXTXBUF0Text Word 0 XOR Buffer Word 0Go
A4hTXTXBUF1Text Word 1 XOR Buffer Word 1Go
A8hTXTXBUF2Text Word 2 XOR Buffer Word 2Go
AChTXTXBUF3Text Word 3 XOR Buffer Word3Go
104hIMASKInterrupt Mask registerGo
108hRISRaw Interrupt Status registerGo
10ChMISMasked Interrupt Status registerGo
110hISETInterrupt Set registerGo
114hICLRInterrupt Clear registerGo
118hIMSETInterrupt Mask Set registerGo
11ChIMCLRInterrupt Mask Clear registerGo

Complex bit access types are encoded to fit into small table cells. Table 16-2 shows the codes that are used for access types in this section.

Table 16-2 AES Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
RHR
H		Read
Set or cleared by hardware
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

16.4.1 DESC Register (Offset = 0h) [Reset = 6B424010h]

DESC is shown in Table 16-3.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 16-3 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDR6B42hModule Identifier
This register is used to uniquely identify this IP.
15-12STDIPOFFR4hStandard IP MMR block offset
Standard IP MMRs are the set from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist.
0x1-0xF: Standard IP MMRs begin at offset of 64*STDIPOFF from the base IP address.
11-8INSTIDXR0hIP Instance ID number
If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15)
3-0MINREVR0hMinor Revision of IP(0-15)

16.4.2 TRG Register (Offset = 10h) [Reset = 00000000h]

TRG is shown in Table 16-4.

Return to the Summary Table.

Trigger
This register is used to manually trigger operations.

Table 16-4 TRG Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3DMACHAW0hManually trigger channel A request
0h = Writing 0 has no effect
1h = Triggers channel A request
2DMACHBW0hManually trigger channel B request
0h = Writing 0 has no effect
1h = Triggers channel B request
1-0AESOPW0hAES Operation
Write an enumerated value to this field when STA.STATE = IDLE to manually trigger an AES operation. If condition is not met, the trigger is ignored. Non-enumerated values are ignored.
Enumerated value indicates source of AES operation
1h = TXT = AES(KEY,TXT)
2h = TXT = AES(KEY,BUF)
3h = TXT = AES(KEY, TXT XOR BUF)

16.4.3 ABORT Register (Offset = 14h) [Reset = 00000000h]

ABORT is shown in Table 16-5.

Return to the Summary Table.

Abort
This register is used to abort current AES operation.

Table 16-5 ABORT Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0ABORTAESW0hAbort AES operation
Abort an ongoing AES operation. An abort will clear TXT, BUF, DMA, AUTOCFG registers
0h = Writing 0 has no effect
1h = Aborts an ongoing AES operation

16.4.4 CLR Register (Offset = 18h) [Reset = 00000000h]

CLR is shown in Table 16-6.

Return to the Summary Table.

Clear
This register is used to clear contents of TXT and BUF when STA.STATE = IDLE. If condition is not met, the contents remain unchanged.

Table 16-6 CLR Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1TXTW0hClear TXT
0h = Writing 0 has no effect
1h = Clears TXT
0BUFW0hClear BUF
0h = Writing 0 has no effect
1h = Clears BUF

16.4.5 STA Register (Offset = 1Ch) [Reset = 00000000h]

STA is shown in Table 16-7.

Return to the Summary Table.

Status
This register provides information on AES accellerator state and BUF status.

Table 16-7 STA Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1BUFSTAR0h BUF Status
Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGAES = WRBUF3.
If AUTOCFG.TRGAES != WRBUF3, then STA.BUFSTA will hold the value 0.
Note : Useful for CBC-MAC
0h = Data stored in BUF is already consumed by the AES engine and next block of data can be written in BUF.
1h = Data stored in BUF is not yet consumed by the AES engine. Next block of data cannot be written into BUF until STA.STATE = IDLE.
0STATER0hState
Field gives the state of the AES engine.
0h = AES engine is IDLE
1h = AES operation active

16.4.6 DMA Register (Offset = 20h) [Reset = 00000000h]

DMA is shown in Table 16-8.

Return to the Summary Table.

Direct Memory Access
This register controls the conditions that will generate burst requests on each DMA channel.

Table 16-8 DMA Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-16DONEACTR/W0hDone Action
This field determines the side effects of DMA done. It is allowed to configure this field with an OR-combination of supported enums, with the exception that GATE_TRGAES_ON_CHA and GATE_TRGAES_ON_CHA_DEL must be mutually exclusive
0h = DMA done has no side effect
1h = Triggers defined in AUTOCFG.TRGAES are gated when RIS.CHADONE = SET
2h = Delayed gating of triggers defined in AUTOCFG.TRGAES
Due to the pipelining of BUF writes, in certain modes, DMA CHA Done appears before the last but one AES operation has completed. Setting this bit, will gate the triggers defined in AUTOCFG.TRGAES only after the last write by CHA is consumed by AES FSM. Used in ECB,CBC,CBC-MAC modes (having multiple blocks encryption/decryption) to avoid spurious AES operation triggered on last read by CHB. For single mode operation, DMA.GATE_TRGAES_ON_CHA must be used.
4h = DMA channel A done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.
8h = DMA channel B done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met.
15-14RESERVEDR0hReserved
13-12ADRCHBR/W0hChannel B Read Write Address
The DMA accesses DMACHB to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration.
0h = Start address is TXT0
1h = Start address is TXTX0
2h = Start address is BUF0
3h = Start address is TXTXBUF0
11RESERVEDR0hReserved
10-8TRGCHBR/W0hChannel B Trigger
Select the condition that triggers DMA channel B request. Non-enumerated values are not supported and ignored.
0h = DMA requests are disabled
1h = Start of AES operation triggers request
2h = Completion of AES operation triggers request
3h = Writes to TXT3, TXTX3, or TXTXBUF3 trigger request
4h = Reads of TXT3, or TXTXBUF3 trigger request
7-6RESERVEDR0hReserved
5-4ADRCHAR/W0hChannel A Read Write Address
The DMA accesses DMACHA to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration.
0h = Start address is TXT0
1h = Start address is TXTX0
2h = Start address is BUF0
3h = Start address is TXTXBUF0
3RESERVEDR0hReserved
2-0TRGCHAR/W0hChannel A Trigger
Select the condition that triggers DMA channel A request. Non-enumerated values are not supported and ignored.
0h = DMA requests are disabled
1h = Start of AES operation triggers request
2h = Completion of AES operation triggers request
3h = Writes to TXT3 or TXTX3 trigger request
4h = Reads of TXT3 or TXTXBUF3 trigger request

16.4.7 DMACHA Register (Offset = 24h) [Reset = 00000000h]

DMACHA is shown in Table 16-9.

Return to the Summary Table.

DMA Channel A data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHA.

Table 16-9 DMACHA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hValue transferred through DMA Channel A

16.4.8 DMACHB Register (Offset = 28h) [Reset = 00000000h]

DMACHB is shown in Table 16-10.

Return to the Summary Table.

DMA Channel B data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHB.

Table 16-10 DMACHB Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hValue transferred through DMA Channel B

16.4.9 AUTOCFG Register (Offset = 2Ch) [Reset = 00000000h]

AUTOCFG is shown in Table 16-11.

Return to the Summary Table.

Automatic Configuration
This register configures automatic hardware updates to TXT and BUF. Configure this register to reduce software overhead during cipher modes.

Table 16-11 AUTOCFG Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28CHBDNCLRR/W0hThis field enable auto-clear of RIS.CHBDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

0h = Disable auto-clear of RIS.CHBDONE interrupt
1h = Enable auto-clear of RIS.CHBDONE interrupt
27CHADNCLRR/W0hThis field enables auto-clear of RIS.CHADONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

0h = Disable auto-clear of RIS.CHADONE interrupt
1h = Enable auto-clear of RIS.CHADONE interrupt
26CLRAESSTR/W0hClear AES Start
This field enables auto-clear of RIS.AESSTART interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .
0h = Disable auto-clear of RIS.AESSTART interrupt
1h = Enable auto-clear of RIS.AESSTART interrupt
25CLRAESDNR/W0hClear AES Done
This field enables auto-clear of RIS.AESDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 .

0h = Disable auto-clear of RIS.AESDONE interrupt
1h = Enable auto-clear of RIS.AESDONE interrupt
24BUSHALTR/W0hBus Halt
This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF when STA.STATE = BUSY.
0h = Disable bus halt
When STA.STATE = BUSY, writes to KEY, TXT, TXTX are ignored, reads from TXT, TXTXBUF return zero.
When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, writes to BUF are ignored, reads return zero.
1h = Enable bus halt
When STA.STATE = BUSY, access to KEY, TXT, TXTX, TXTXBUF halt the bus until STA.STATE = IDLE.
When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, access to BUF halts the bus until STA.STATE = IDLE.
23-22RESERVEDR0hReserved
21-19CTRSIZER/W0hCounter Size
Configures size of counter as either 8,16,32,64 or 128
Non-enumerated values are not supported and ignored
0h = Disable CTR operation
1h = Configures counter size as 8-bit
2h = Configures counter size as 16-bit
3h = Configures counter size as 32-bit
4h = Configures counter size as 64-bit
5h = Configures counter size as 128-bit
18CTRALIGNR/W0hCounter Alignment
Specifies alignment of counter
0h = Indicates Left Aligned Counter
Not applicable for 128-bit counter size.
For 128-bit counter, all octets will be considered
When left aligned,,octet 0-7 will be considered , based on counter size and endianness
1h = Indicates right aligned counter
Not applicable when counter size is 128-bit
For 128-bit counter, all octets will be considered
If right aligned, octet 8-15 will be considered based on endianness and counter size
17CTRENDNR/W0hCounter Endianness
Specifies Endianness of counter
0h = Specifies Little Endian Counter
Carry will flow from octet 'n' to octet 'n+1'
1h = Specifies Big Endian Counter
Carry will flow from octet 'n' to octet 'n-1'
16-10RESERVEDR0hReserved
9-8TRGTXTR/W0hTrigger for TXT
This field determines if and when hardware automatically XORs BUF into TXT. Non-enumerated values are not supported and ignored. It is allowed to configure this field with an OR-combination of supported enums.
0h = No hardware update of TXT
1h = Hardware XORs content of BUF into TXT upon read of TXT3
2h = Hardware XORs content of BUF into TXT upon read of TXTXBUF3
7-6RESERVEDR0hReserved
5-4AESSRCR/W0hAES Source
This field specifies the data source to hardware-triggered AES operations. Non-enumerated values are not supported and ignored.
1h = TXT = AES(KEY,TXT)
2h = TXT = AES(KEY,BUF)
3h = TXT = AES(KEY, TXT XOR BUF)
3-0TRGAESRH/W0hTrigger Electronic Codebook
This field specifies one or more actions that indirectly trigger AES operation.
It is allowed to configure this field with an OR-combination of supported enums.
0h = No user action indirectly triggers AES operation
1h = All writes to TXT3 or TXTX3 trigger action, only when STA.STATE = IDLE
2h = All reads of TXT3 or TXTXBUF3 trigger action, only when STA.STATE = IDLE
4h = All writes to BUF3 will schedule to trigger action once STA.STATE is or becomes IDLE, only when AUTOCFG.CTRSIZE = DIS
8h = Write to BUF3 will schedule to trigger single action once STA.STATE is or becomes IDLE. Subsequent writes do not trigger action unless this setting is written again to this field.

16.4.10 KEY0 Register (Offset = 50h) [Reset = 00000000h]

KEY0 is shown in Table 16-12.

Return to the Summary Table.

Key Word 0
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 16-12 KEY0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[31:0]

16.4.11 KEY1 Register (Offset = 54h) [Reset = 00000000h]

KEY1 is shown in Table 16-13.

Return to the Summary Table.

Key Word 1
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 16-13 KEY1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[63:32]

16.4.12 KEY2 Register (Offset = 58h) [Reset = 00000000h]

KEY2 is shown in Table 16-14.

Return to the Summary Table.

Key Word 2
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 16-14 KEY2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[95:64]

16.4.13 KEY3 Register (Offset = 5Ch) [Reset = 00000000h]

KEY3 is shown in Table 16-15.

Return to the Summary Table.

Key Word 3
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.

Table 16-15 KEY3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue of KEY[127:96]

16.4.14 TXT0 Register (Offset = 70h) [Reset = 00000000h]

TXT0 is shown in Table 16-16.

Return to the Summary Table.

Text Word 0
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 16-16 TXT0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[31:0]

16.4.15 TXT1 Register (Offset = 74h) [Reset = 00000000h]

TXT1 is shown in Table 16-17.

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Text Word 1
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 16-17 TXT1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[63:32]

16.4.16 TXT2 Register (Offset = 78h) [Reset = 00000000h]

TXT2 is shown in Table 16-18.

Return to the Summary Table.

Text Word 2
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 16-18 TXT2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[95:64]

16.4.17 TXT3 Register (Offset = 7Ch) [Reset = 00000000h]

TXT3 is shown in Table 16-19.

Return to the Summary Table.

Text Word 3
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.

Table 16-19 TXT3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of TXT[127:96]
AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation.

16.4.18 TXTX0 Register (Offset = 80h) [Reset = 00000000h]

TXTX0 is shown in Table 16-20.

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Text Word 0 XOR
Write data to this register to XOR data with contents in TXT0.VAL.

Table 16-20 TXTX0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT0 will be TXT0.VAL = VAL XOR TXT0.VAL

16.4.19 TXTX1 Register (Offset = 84h) [Reset = 00000000h]

TXTX1 is shown in Table 16-21.

Return to the Summary Table.

Text Word 1 XOR
Write data to this register to XOR data with contents in TXT1.VAL.

Table 16-21 TXTX1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT1 will be TXT1.VAL = VAL XOR TXT1.VAL

16.4.20 TXTX2 Register (Offset = 88h) [Reset = 00000000h]

TXTX2 is shown in Table 16-22.

Return to the Summary Table.

Text Word 2 XOR
Write data to this register to XOR data with contents in TXT2.VAL.

Table 16-22 TXTX2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT2 will be TXT2.VAL = VAL XOR TXT2.VAL

16.4.21 TXTX3 Register (Offset = 8Ch) [Reset = 00000000h]

TXTX3 is shown in Table 16-23.

Return to the Summary Table.

Text Word 3 XOR
Write data to this register to XOR data with contents in TXT3.VAL.
AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation.

Table 16-23 TXTX3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALW0hValue in TXT3 will be TXT3.VAL = VAL XOR TXT3.VAL

16.4.22 BUF0 Register (Offset = 90h) [Reset = 00000000h]

BUF0 is shown in Table 16-24.

Return to the Summary Table.

Buffer Word 0
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 16-24 BUF0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[31:0]

16.4.23 BUF1 Register (Offset = 94h) [Reset = 00000000h]

BUF1 is shown in Table 16-25.

Return to the Summary Table.

Buffer Word 1
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 16-25 BUF1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[63:32]

16.4.24 BUF2 Register (Offset = 98h) [Reset = 00000000h]

BUF2 is shown in Table 16-26.

Return to the Summary Table.

Buffer Word 2
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.

Table 16-26 BUF2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[95:64]

16.4.25 BUF3 Register (Offset = 9Ch) [Reset = 00000000h]

BUF3 is shown in Table 16-27.

Return to the Summary Table.

Buffer Word 3
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
AUTOCFG.TRGAES decides if a write to this field triggers an AES operation.

Table 16-27 BUF3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALRH/W0hValue of BUF[127:96]

16.4.26 TXTXBUF0 Register (Offset = A0h) [Reset = 00000000h]

TXTXBUF0 is shown in Table 16-28.

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Text Word 0 XOR Buffer Word 0
Read this register to obtain plaintext during CFB decryption.

Table 16-28 TXTXBUF0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT0.VAL XOR BUF0.VAL

16.4.27 TXTXBUF1 Register (Offset = A4h) [Reset = 00000000h]

TXTXBUF1 is shown in Table 16-29.

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Text Word 1 XOR Buffer Word 1
Read this register to obtain plaintext during CFB decryption.

Table 16-29 TXTXBUF1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT1.VAL XOR BUF1.VAL

16.4.28 TXTXBUF2 Register (Offset = A8h) [Reset = 00000000h]

TXTXBUF2 is shown in Table 16-30.

Return to the Summary Table.

Text Word 2 XOR Buffer Word 2
Read this register to obtain plaintext during CFB decryption.

Table 16-30 TXTXBUF2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT2.VAL XOR BUF2.VAL

16.4.29 TXTXBUF3 Register (Offset = ACh) [Reset = 00000000h]

TXTXBUF3 is shown in Table 16-31.

Return to the Summary Table.

Text Word 3 XOR Buffer Word3
Read this register to obtain plaintext during CFB decryption.

Table 16-31 TXTXBUF3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hValue read will be TXT3.VAL XOR BUF3.VAL

16.4.30 IMASK Register (Offset = 104h) [Reset = 00000000h]

IMASK is shown in Table 16-32.

Return to the Summary Table.

Interrupt Mask register

Table 16-32 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER/W0hDMA Channel B Done interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask
2CHADONER/W0hDMA Channel A Done interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask
1AESSTARTR/W0hAES Start interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask
0AESDONER/W0hAES Done interrupt mask
0h = Disable interrupt mask
1h = Enable interrupt mask

16.4.31 RIS Register (Offset = 108h) [Reset = 00000000h]

RIS is shown in Table 16-33.

Return to the Summary Table.

Raw Interrupt Status register

Table 16-33 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER0hRaw Interrupt Status for DMA Channel B Done
0h = Interrupt did not occur
1h = Interrupt occurred
2CHADONER0hRaw Interrupt Status for DMA Channel A Done
0h = Interrupt did not occur
1h = Interrupt occurred
1AESSTARTR0hRaw Interrupt Status for AES Start
0h = Interrupt did not occur
1h = Interrupt occurred
0AESDONER0hRaw Interrupt Status for AES Done
0h = Interrupt did not occur
1h = Interrupt occurred

16.4.32 MIS Register (Offset = 10Ch) [Reset = 00000000h]

MIS is shown in Table 16-34.

Return to the Summary Table.

Masked Interrupt Status register

Table 16-34 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONER0hMasked Interrupt Status for DMA Channel B Done
0h = Interrupt did not occur
1h = Interrupt occurred
2CHADONER0hMasked Interrupt Status for DMA Channel A Done
0h = Interrupt did not occur
1h = Interrupt occurred
1AESSTARTR0hMasked Interrupt Status for AES Start
0h = Interrupt did not occur
1h = Interrupt occurred
0AESDONER0hMasked Interrupt Status for AES Done
0h = Interrupt did not occur
1h = Interrupt occurred

16.4.33 ISET Register (Offset = 110h) [Reset = 00000000h]

ISET is shown in Table 16-35.

Return to the Summary Table.

Interrupt Set register

Table 16-35 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hSet DMA Channel B Done interrupt
0h = Writing 0 has no effect
1h = Set interrupt
2CHADONEW0hSet DMA Channel A Done interrupt
0h = Writing 0 has no effect
1h = Set interrupt
1AESSTARTW0hSet AES Start interrupt
0h = Writing 0 has no effect
1h = Set interrupt
0AESDONEW0hSet AES Done interrupt
0h = Writing 0 has no effect
1h = Set interrupt

16.4.34 ICLR Register (Offset = 114h) [Reset = 00000000h]

ICLR is shown in Table 16-36.

Return to the Summary Table.

Interrupt Clear register

Table 16-36 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hClear DMA Channel B Done interrupt
0h = Writing 0 has no effect
1h = Clear interrupt
2CHADONEW0hClear DMA Channel A Done interrupt
0h = Writing 0 has no effect
1h = Clear interrupt
1AESSTARTW0hClear AES Start interrupt
0h = Writing 0 has no effect
1h = Clear interrupt
0AESDONEW0hClear AES Done interrupt
0h = Writing 0 has no effect
1h = Clear interrupt

16.4.35 IMSET Register (Offset = 118h) [Reset = 00000000h]

IMSET is shown in Table 16-37.

Return to the Summary Table.

Interrupt Mask Set register

Table 16-37 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hSet DMA Channel B Done interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
2CHADONEW0hSet DMA Channel A Done interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
1AESSTARTW0hSet AES Start interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask
0AESDONEW0hSet AES Done interrupt mask
0h = Writing 0 has no effect
1h = Set interrupt mask

16.4.36 IMCLR Register (Offset = 11Ch) [Reset = 00000000h]

IMCLR is shown in Table 16-38.

Return to the Summary Table.

Interrupt Mask Clear register

Table 16-38 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3CHBDONEW0hClear DMA Channel B Done interrupt mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
2CHADONEW0hClear DMA Channel A Done interrupt mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
1AESSTARTW0hClear AES Start interrupt mask
0h = Writing 0 has no effect
1h = Clear interrupt mask
0AESDONEW0hClear AES Done interrupt mask
0h = Writing 0 has no effect
1h = Clear interrupt mask