SWCU193A April   2023  – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 Flash
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  4. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 Reset
      2. 6.4.2 Shutdown
      3. 6.4.3 Active
      4. 6.4.4 Idle
      5. 6.4.5 Standby
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  9. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 Flash
        1. 7.2.4.1 Flash Read-Only Protection
        2. 7.2.4.2 Flash Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  10. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 8.2.4.5 Debug Flow Charts
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  11. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  12. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Deadband
      6. 10.4.6 Deadband, Fault, and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  13. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  14. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  15. 13Low Power Comparator and SYS0
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-Up
    4. 13.4 SYS0 Registers
  16. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  17. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  18. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  19. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power-Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA and FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-Hoc Single Conversion
    5. 17.5 ADC Registers
  20. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  21. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  22. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  23. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  24. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-Domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers
  25. 23Revision History

17.5 ADC Registers

Table 17-8 lists the memory-mapped registers for the ADC registers. All register offset addresses not listed in Table 17-8 should be considered as reserved locations and the register contents should not be modified.

Table 17-8 ADC Registers
OffsetAcronymRegister NameSection
28hIMASK0Interrupt maskGo
30hRIS0Raw interrupt statusGo
38hMIS0Masked interrupt statusGo
40hISET0Interrupt setGo
48hICLR0Interrupt clearGo
58hIMASK1Interrupt maskGo
60hRIS1Raw interrupt statusGo
68hMIS1Masked interrupt statusGo
70hISET1Interrupt setGo
78hICLR1Interrupt clearGo
88hIMASK2Interrupt maskGo
90hRIS2Raw interrupt statusGo
98hMIS2Masked interrupt statusGo
A0hISET2Interrupt setGo
A8hICLR2Interrupt clearGo
100hCTL0Control Register 0Go
104hCTL1Control Register 1Go
108hCTL2Control Register 2Go
10ChCTL3Control Register 3Go
114hSCOMP0Sample Time Compare 0 RegisterGo
118hSCOMP1Sample Time Compare 1 RegisterGo
11ChREFCFGReference Buffer Configuration RegisterGo
148hWCLOWWindow Comparator Low Threshold RegisterGo
150hWCHIGHWindow Comparator High Threshold RegisterGo
160hFIFODATAFIFO Data RegisterGo
170hASCRESASC Result RegisterGo
180hMEMCTL0Conversion Memory Control Register 0Go
184hMEMCTL1Conversion Memory Control Register 1Go
188hMEMCTL2Conversion Memory Control Register 2Go
18ChMEMCTL3Conversion Memory Control Register 3Go
280hMEMRES0Memory Result Register 0Go
284hMEMRES1Memory Result Register 1Go
288hMEMRES2Memory Result Register 2Go
28ChMEMRES3Memory Result Register 3Go
340hSTAStatus RegisterGo
E00hTEST0Internal. Only to be used through TI provided API.Go
E08hTEST2Internal. Only to be used through TI provided API.Go
E0ChTEST3Internal. Only to be used through TI provided API.Go
E10hTEST4Internal. Only to be used through TI provided API.Go
E14hTEST5Internal. Only to be used through TI provided API.Go
E18hTEST6Internal. Only to be used through TI provided API.Go
E20hDEBUG1Internal. Only to be used through TI provided API.Go
E24hDEBUG2Internal. Only to be used through TI provided API.Go
E28hDEBUG3Internal. Only to be used through TI provided API.Go
E2ChDEBUG4Internal. Only to be used through TI provided API.Go

Complex bit access types are encoded to fit into small table cells. Table 17-9 shows the codes that are used for access types in this section.

Table 17-9 ADC Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

17.5.1 IMASK0 Register (Offset = 28h) [Reset = 00000000h]

IMASK0 is shown in Table 17-10.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 17-10 IMASK0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMEMRES3 conversion result interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
10MEMRESIFG2R/W0hMEMRES2 conversion result interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
9MEMRESIFG1R/W0hMEMRES1 conversion result interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
7ASCDONER/W0hMask for ASC done raw interrupt flag.
0h = Disable interrupt mask
1h = Enable interrupt mask
6UVIFGR/W0hConversion underflow interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
5DMADONER/W0hDMA done interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
4INIFGR/W0hIn-range comparator interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
3LOWIFGR/W0hLow threshold compare interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
2HIGHIFGR/W0hHigh threshold compare interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
1TOVIFGR/W0hSequence conversion time overflow interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask
0OVIFGR/W0hConversion overflow interrupt mask.
0h = Disable interrupt mask
1h = Enable interrupt mask

17.5.2 RIS0 Register (Offset = 30h) [Reset = 00000000h]

RIS0 is shown in Table 17-11.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 17-11 RIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR0 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER/W0hRaw interrupt flag for ASC done.
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hRaw interrupt flag for MEMRESx underflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hRaw interrupt flag for DMADONE.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hRaw interrupt status for In-range comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hRaw interrupt flag for sequence conversion trigger overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hRaw interrupt flag for MEMRESx overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.

17.5.3 MIS0 Register (Offset = 38h) [Reset = 00000000h]

MIS0 is shown in Table 17-12.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 17-12 MIS0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMasked interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hMasked interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hMasked interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hMasked interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER/W0hMasked interrupt status for ASC done.
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hMasked interrupt flag for MEMRESx underflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hMasked interrupt flag for DMADONE.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hMask INIFG in MIS0 register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hMasked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hMasked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hMasked interrupt flag for sequence conversion timeout overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hMasked interrupt flag for MEMRESx overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.

17.5.4 ISET0 Register (Offset = 40h) [Reset = 00000000h]

ISET0 is shown in Table 17-13.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 17-13 ISET0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hSet interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hSet interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hSet interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hSet Interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER/W0hSet interrupt for ASC done.
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hSet interrupt for MEMRESx underflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hSet interrupt for DMADONE.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hSet INIFG interrupt register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hSet interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hSet Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hSet interrupt for sequence conversion timeout overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hSet Interrupt for MEMRESx overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.

17.5.5 ICLR0 Register (Offset = 48h) [Reset = 00000000h]

ICLR0 is shown in Table 17-14.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 17-14 ICLR0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hClear interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hClear interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hClear interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hClear interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7ASCDONER/W0hClear ASC done flag in RIS.
0h = Interrupt is not pending.
1h = Interrupt is pending.
6UVIFGR/W0hClear interrupt flag for MEMRESx underflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
5DMADONER/W0hClear interrupt flag for DMADONE.
0h = Interrupt is not pending.
1h = Interrupt is pending.
4INIFGR/W0hClear INIFG in MIS0 register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hClear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hClear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1TOVIFGR/W0hClear interrupt flag for sequence conversion timeout overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.
0OVIFGR/W0hClear interrupt flag for MEMRESx overflow.
0h = Interrupt is not pending.
1h = Interrupt is pending.

17.5.6 IMASK1 Register (Offset = 58h) [Reset = 00000000h]

IMASK1 is shown in Table 17-15.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 17-15 IMASK1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hIn-range comparator interrupt mask.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hLow threshold compare interrupt mask.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hHigh threshold compare interrupt mask.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0hReserved

17.5.7 RIS1 Register (Offset = 60h) [Reset = 00000000h]

RIS1 is shown in Table 17-16.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 17-16 RIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR1 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hRaw interrupt status for In-range comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hRaw interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hRaw interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0hReserved

17.5.8 MIS1 Register (Offset = 68h) [Reset = 00000000h]

MIS1 is shown in Table 17-17.

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Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 17-17 MIS1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hMasked interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hMask INIFG in MIS1 register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hMasked interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hMasked interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0hReserved

17.5.9 ISET1 Register (Offset = 70h) [Reset = 00000000h]

ISET1 is shown in Table 17-18.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 17-18 ISET1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hSet Interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hSet INIFG interrupt register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hSet interrupt for MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hSet Interrupt for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0hReserved

17.5.10 ICLR1 Register (Offset = 78h) [Reset = 00000000h]

ICLR1 is shown in Table 17-19.

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Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 17-19 ICLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0hReserved
8MEMRESIFG0R/W0hClear interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-5RESERVEDR0hReserved
4INIFGR/W0hClear INIFG in MIS1 register.
0h = Interrupt is not pending.
1h = Interrupt is pending.
3LOWIFGR/W0hClear interrupt flag for the MEMRESx result register being below than the WCLOWx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
2HIGHIFGR/W0hClear interrupt flag for the MEMRESx result register being higher than the WCHIGHx threshold of the window comparator.
0h = Interrupt is not pending.
1h = Interrupt is pending.
1-0RESERVEDR0hReserved

17.5.11 IMASK2 Register (Offset = 88h) [Reset = 00000000h]

IMASK2 is shown in Table 17-20.

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Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS0 to MIS0 when the corresponding bit-fields are set to 1.

Table 17-20 IMASK2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMEMRES3 conversion result interrupt mask.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hMEMRES2 conversion result interrupt mask.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hMEMRES1 conversion result interrupt mask.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hMEMRES0 conversion result interrupt mask.
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

17.5.12 RIS2 Register (Offset = 90h) [Reset = 00000000h]

RIS2 is shown in Table 17-21.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR0 register bit.

Table 17-21 RIS2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hRaw interrupt status for MEMRES3.
This bit is set to 1 when MEMRES3 is loaded with a new
conversion result.
Reading MEMRES3 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hRaw interrupt status for MEMRES2.
This bit is set to 1 when MEMRES2 is loaded with a new
conversion result.
Reading MEMRES2 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hRaw interrupt status for MEMRES1.
This bit is set to 1 when MEMRES1 is loaded with a new
conversion result.
Reading MEMRES1 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hRaw interrupt status for MEMRES0.
This bit is set to 1 when MEMRES0 is loaded with a new
conversion result.
Reading MEMRES0 register will clear this bit, or when the
corresponding bit in ICLR2 is set to 1
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

17.5.13 MIS2 Register (Offset = 98h) [Reset = 00000000h]

MIS2 is shown in Table 17-22.

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Extension of Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 17-22 MIS2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hMasked interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hMasked interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hMasked interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hMasked interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

17.5.14 ISET2 Register (Offset = A0h) [Reset = 00000000h]

ISET2 is shown in Table 17-23.

Return to the Summary Table.

Interrupt set register. This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 17-23 ISET2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hSet interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hSet interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hSet interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hSet Interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

17.5.15 ICLR2 Register (Offset = A8h) [Reset = 00000000h]

ICLR2 is shown in Table 17-24.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 17-24 ICLR2 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11MEMRESIFG3R/W0hClear interrupt status for MEMRES3.
0h = No new data ready.
1h = A new data is ready to be read.
10MEMRESIFG2R/W0hClear interrupt status for MEMRES2.
0h = No new data ready.
1h = A new data is ready to be read.
9MEMRESIFG1R/W0hClear interrupt status for MEMRES1.
0h = No new data ready.
1h = A new data is ready to be read.
8MEMRESIFG0R/W0hClear interrupt status for MEMRES0.
0h = No new data ready.
1h = A new data is ready to be read.
7-0RESERVEDR0hReserved

17.5.16 CTL0 Register (Offset = 100h) [Reset = 00000000h]

CTL0 is shown in Table 17-25.

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Control Register 0

Table 17-25 CTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDR0hReserved
26-24SCLKDIVR/W0hSample clock divider
0h = Do not divide clock source
1h = Divide clock source by 2
2h = Divide clock source by 4
3h = Divide clock source by 8
4h = Divide clock source by 16
5h = Divide clock source by 24
6h = Divide clock source by 32
7h = Divide clock source by 48
23-17RESERVEDR0hReserved
16PWRDNR/W0hPower down policy
0h = ADC is powered down on completion of a conversion if there is no pending trigger
1h = ADC remains powered on as long as it is enabled through software.
15-1RESERVEDR0hReserved
0ENCR/W0hEnable conversion
0h = Conversion disabled. ENC change from ON to OFF will abort single or repeat sequence on a MEMCTLx boundary. The current conversion will finish and result stored in corresponding MEMRESx.
1h = Conversion enabled. ADC sequencer waits for the programmed trigger (software or hardware).

17.5.17 CTL1 Register (Offset = 104h) [Reset = 00000000h]

CTL1 is shown in Table 17-26.

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Control Register 1

Table 17-26 CTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0hReserved
20SAMPMODER/W0hSample mode. This bit selects the source of the sampling signal.
MANUAL option is not applicable when TRIGSRC is selected as hardware event trigger.
0h = Sample timer high phase is used as sample signal
1h = Software trigger is used as sample signal
19-18RESERVEDR0hReserved
17-16CONSEQR/W0hConversion sequence mode
0h = ADC channel in MEMCTLx pointed by STARTADD will be converted once
1h = ADC channel sequence pointed by STARTADD and ENDADD will be converted once
2h = ADC channel in MEMCTLx pointed by STARTADD will be converted repeatedly
3h = ADC channel sequence pointed by STARTADD and ENDADD will be converted repeatedly
15-9RESERVEDR0hReserved
8SCR/W0hStart of conversion
0h = When SAMPMODE is set to MANUAL, clearing this bit will end the sample phase and the conversion phase will start.
When SAMPMODE is set to AUTO, writing 0 has no effect.
1h = When SAMPMODE is set to MANUAL, setting this bit will start the sample phase. Sample phase will last as long as this bit is set.
When SAMPMODE is set to AUTO, setting this bit will trigger the timer based sample time.
7-1RESERVEDR0hReserved
0TRIGSRCR/W0hSample trigger source
0h = Software trigger
1h = Hardware event trigger

17.5.18 CTL2 Register (Offset = 108h) [Reset = 00000000h]

CTL2 is shown in Table 17-27.

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Control Register 2

Table 17-27 CTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28-24ENDADDR/W0hSequence end address. These bits select which MEMCTLx is the last one for the sequence mode.
The value of ENDADD is 0x00 to 0x03 corresponding to MEMRES0 to MEMRES3.
0h = MEMCTL0 is selected as end address of sequence.
1h = MEMCTL1 is selected as end address of sequence.
2h = MEMCTL2 is selected as end address of sequence.
3h = MEMCTL3 is selected as end address of sequence.
23-21RESERVEDR0hReserved
20-16STARTADDR/W0hSequencer start address. These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode.
The value of STARTADD is 0x00 to 0x17, corresponding to MEMRES0 to MEMRES23.
0h = MEMCTL0 is selected as start address of a sequence or for a single conversion.
1h = MEMCTL1 is selected as start address of a sequence or for a single conversion.
2h = MEMCTL2 is selected as start address of a sequence or for a single conversion.
3h = MEMCTL3 is selected as start address of a sequence or for a single conversion.
15-11RESERVEDR0hReserved
10FIFOENR/W0hEnable FIFO based operation
0h = Disable
1h = Enable
9RESERVEDR0hReserved
8DMAENR/W0hEnable DMA trigger for data transfer.
Note: DMAEN bit is cleared by hardware based on DMA done signal at the end of data transfer. Software has to re-enable DMAEN bit for ADC to generate DMA triggers.
0h = DMA trigger not enabled
1h = DMA trigger enabled
7-3RESERVEDR0hReserved
2-1RESR/W0hResolution. These bits define the resolutoin of ADC conversion result.
Note : A value of 3 defaults to 12-bits resolution.
0h = 12-bits resolution
1h = 10-bits resolution
2h = 8-bits resolution
0DFR/W0hData read-back format. Data is always stored in binary unsigned format.
0h = Digital result reads as Binary Unsigned.
1h = Digital result reads Signed Binary. (2s complement), left aligned.

17.5.19 CTL3 Register (Offset = 10Ch) [Reset = 00000000h]

CTL3 is shown in Table 17-28.

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Control Register 3. This register is used to configure ADC for ad-hoc single conversion.

Table 17-28 CTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0hReserved
13-12ASCVRSELR/W0hSelects voltage reference for ASC operation. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDS reference
1h = External reference from AREF+/AREF- pins
2h = Internal reference
11-9RESERVEDR0hReserved
8ASCSTIMER/W0hASC sample time compare value select. This is used to select between SCOMP0 and SCOMP1 registers for ASC operation.
0h = Select SCOMP0
1h = Select SCOMP1
7-5RESERVEDR0hReserved
4-0ASCCHSELR/W0hASC channel select
0h = Selects channel 0
1h = Selects channel 1
2h = Selects channel 2
3h = Selects channel 3
4h = Selects channel 4
5h = Selects channel 5
6h = Selects channel 6
7h = Selects channel 7
8h = Selects channel 8
9h = Selects channel 9
Ah = Selects channel 10
Bh = Selects channel 11
Ch = Selects channel 12
Dh = Selects channel 13
Eh = Selects channel 14
Fh = Selects channel 15

17.5.20 SCOMP0 Register (Offset = 114h) [Reset = 00000000h]

SCOMP0 is shown in Table 17-29.

Return to the Summary Table.

Sample time compare 0 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.

Table 17-29 SCOMP0 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

17.5.21 SCOMP1 Register (Offset = 118h) [Reset = 00000000h]

SCOMP1 is shown in Table 17-30.

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Sample time compare 1 register. Specifies the sample time, in number of ADC sample clock cycles. CTL0.ENC must be set to 0 to write to this register.

Table 17-30 SCOMP1 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0VALR/W0hSpecifies the number of sample clocks.
When VAL = 0 or 1, number of sample clocks = Sample clock divide value.
When VAL > 1, number of sample clocks = VAL x Sample clock divide value.
Note: Sample clock divide value is not the value written to SCLKDIV but the actual divide value (SCLKDIV = 2 implies divide value is 4).
Example: VAL = 4, SCLKDIV = 3 implies 32 sample clock cycles.

17.5.22 REFCFG Register (Offset = 11Ch) [Reset = 00000000h]

REFCFG is shown in Table 17-31.

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Reference buffer configuration register

Table 17-31 REFCFG Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR0hReserved
4-3IBPROGR/W0hConfigures reference buffer bias current output value
0h = 1uA
1h = 0.5uA
2h = 2uA
3h = 0.67uA
2SPARER/W0hSpare bit
1REFVSELR/W0hConfigures reference buffer output voltage
0h = REFBUF generates 2.5V output
1h = REFBUF generates 1.4V output
0REFENR/W0hReference buffer enable
0h = Disable
1h = Enable

17.5.23 WCLOW Register (Offset = 148h) [Reset = 00000000h]

WCLOW is shown in Table 17-32.

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Window Comparator Low Threshold Register.
The data format that is used to write and read WCLOW depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCLOW.

Table 17-32 WCLOW Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The value based on the resolution has to be right aligned with the MSB on the left.
For 10-bits and 8-bits resolution, unused bits have to be 0s.
If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bits have to be 0s.

17.5.24 WCHIGH Register (Offset = 150h) [Reset = 00000000h]

WCHIGH is shown in Table 17-33.

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Window Comparator High Threshold Register.
The data format that is used to write and read WCHIGH depends on the value of DF bit in CTL2 register.
CTL0.ENC must be 0 to write to this register.
Note: Change in ADC data format or resolution does not reset WCHIGH.

Table 17-33 WCHIGH Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary format has to be used.
The threshold value has to be right aligned, with the MSB on the left.
For 10-bits and 8-bits resolution, unused bit have to be 0s.
If DF = 1, 2s-complement format has to be used.
The value based on the resolution has to be left aligned with the LSB on the right.
For 10-bits and 8-bits resolution, unused bit have to be 0s.

17.5.25 FIFODATA Register (Offset = 160h) [Reset = 00000000h]

FIFODATA is shown in Table 17-34.

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FIFO data register. This is a virtual register used to read from FIFO.

Table 17-34 FIFODATA Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hRead from this data field returns the ADC sample from FIFO.

17.5.26 ASCRES Register (Offset = 170h) [Reset = 00000000h]

ASCRES is shown in Table 17-35.

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ASC result register

Table 17-35 ASCRES Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR0hResult of ADC ad-hoc single conversion.
If DF = 0, unsigned binary:
The conversion result is right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion result is left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

17.5.27 MEMCTL0 Register (Offset = 180h) [Reset = 00000000h]

MEMCTL0 is shown in Table 17-36.

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Conversion Memory Control Register 0.
CTL0.ENC must be set to 0 to write to this register.

Table 17-36 MEMCTL0 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDS reference
1h = External reference from AREF+/AREF- pins
2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
0h = Selects channel 0
1h = Selects channel 1
2h = Selects channel 2
3h = Selects channel 3
4h = Selects channel 4
5h = Selects channel 5
6h = Selects channel 6
7h = Selects channel 7
8h = Selects channel 8
9h = Selects channel 9
Ah = Selects channel 10
Bh = Selects channel 11
Ch = Selects channel 12
Dh = Selects channel 13
Eh = Selects channel 14
Fh = Selects channel 15

17.5.28 MEMCTL1 Register (Offset = 184h) [Reset = 00000000h]

MEMCTL1 is shown in Table 17-37.

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Conversion Memory Control Register 1.
CTL0.ENC must be set to 0 to write to this register.

Table 17-37 MEMCTL1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDS reference
1h = External reference from AREF+/AREF- pins
2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
0h = Selects channel 0
1h = Selects channel 1
2h = Selects channel 2
3h = Selects channel 3
4h = Selects channel 4
5h = Selects channel 5
6h = Selects channel 6
7h = Selects channel 7
8h = Selects channel 8
9h = Selects channel 9
Ah = Selects channel 10
Bh = Selects channel 11
Ch = Selects channel 12
Dh = Selects channel 13
Eh = Selects channel 14
Fh = Selects channel 15

17.5.29 MEMCTL2 Register (Offset = 188h) [Reset = 00000000h]

MEMCTL2 is shown in Table 17-38.

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Conversion Memory Control Register 2.
CTL0.ENC must be set to 0 to write to this register.

Table 17-38 MEMCTL2 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDS reference
1h = External reference from AREF+/AREF- pins
2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
0h = Selects channel 0
1h = Selects channel 1
2h = Selects channel 2
3h = Selects channel 3
4h = Selects channel 4
5h = Selects channel 5
6h = Selects channel 6
7h = Selects channel 7
8h = Selects channel 8
9h = Selects channel 9
Ah = Selects channel 10
Bh = Selects channel 11
Ch = Selects channel 12
Dh = Selects channel 13
Eh = Selects channel 14
Fh = Selects channel 15

17.5.30 MEMCTL3 Register (Offset = 18Ch) [Reset = 00000000h]

MEMCTL3 is shown in Table 17-39.

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Conversion Memory Control Register 3.
CTL0.ENC must be set to 0 to write to this register.

Table 17-39 MEMCTL3 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0hReserved
28WINCOMPR/W0hEnable window comparator.
0h = Disable
1h = Enable
27-25RESERVEDR0hReserved
24TRGR/W0hTrigger policy. Indicates if a trigger will be needed to step to the next MEMCTL in the sequence or to perform next conversion in the case of repeat single channel conversions.
0h = Next conversion is automatic
1h = Next conversion requires a trigger
23-13RESERVEDR0hReserved
12STIMER/W0hSelects the source of sample timer period between SCOMP0 and SCOMP1.
0h = Select SCOMP0
1h = Select SCOMP1
11-10RESERVEDR0hReserved
9-8VRSELR/W0hVoltage reference selection. AREF- must be connected to on-board ground when external reference option is selected.
Note: Writing value 0x3 defaults to INTREF.
0h = VDDS reference
1h = External reference from AREF+/AREF- pins
2h = Internal reference
7-5RESERVEDR0hReserved
4-0CHANSELR/W0hInput channel select.
0h = Selects channel 0
1h = Selects channel 1
2h = Selects channel 2
3h = Selects channel 3
4h = Selects channel 4
5h = Selects channel 5
6h = Selects channel 6
7h = Selects channel 7
8h = Selects channel 8
9h = Selects channel 9
Ah = Selects channel 10
Bh = Selects channel 11
Ch = Selects channel 12
Dh = Selects channel 13
Eh = Selects channel 14
Fh = Selects channel 15

17.5.31 MEMRES0 Register (Offset = 280h) [Reset = 00000000h]

MEMRES0 is shown in Table 17-40.

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Memory Result Register 0

Table 17-40 MEMRES0 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

17.5.32 MEMRES1 Register (Offset = 284h) [Reset = 00000000h]

MEMRES1 is shown in Table 17-41.

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Memory Result Register 1

Table 17-41 MEMRES1 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

17.5.33 MEMRES2 Register (Offset = 288h) [Reset = 00000000h]

MEMRES2 is shown in Table 17-42.

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Memory Result Register 2

Table 17-42 MEMRES2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

17.5.34 MEMRES3 Register (Offset = 28Ch) [Reset = 00000000h]

MEMRES3 is shown in Table 17-43.

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Memory Result Register 3

Table 17-43 MEMRES3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0DATAR/W0hIf DF = 0, unsigned binary:
The conversion results are right aligned. In 10 and 8 bit modes, the unused MSB bits are forced to 0.
If DF = 1, 2s-complement format:
The conversion results are left aligned. In 10 and 8 bit modes, the unused LSB bits are forced to 0.
The data is stored in the right-justified format and is converted to the left-justified 2s-complement format during read back.

17.5.35 STA Register (Offset = 340h) [Reset = 00000000h]

STA is shown in Table 17-44.

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Status Register

Table 17-44 STA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2ASCACTR0hASC active
0h = Idle or done
1h = ASC active
1RESERVEDR0hReserved
0BUSYR0hBusy. This bit indicates that an active ADC sample or conversion operation is in progress.
0h = No ADC sampling or conversion in progress.
1h = ADC sampling or conversion is in progress.

17.5.36 TEST0 Register (Offset = E00h) [Reset = 00000000h]

TEST0 is shown in Table 17-45.

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Internal. Only to be used through TI provided API.

Table 17-45 TEST0 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0hReserved
30ATEST0_ENR/W0hInternal. Only to be used through TI provided API.
29ATEST1_ENR/W0hInternal. Only to be used through TI provided API.
28-13RESERVEDR0hReserved
12-8ATEST1_MUXSELR/W0hInternal. Only to be used through TI provided API.
7-5RESERVEDR0hReserved
4-0ATEST0_MUXSELR/W0hInternal. Only to be used through TI provided API.

17.5.37 TEST2 Register (Offset = E08h) [Reset = 00000000h]

TEST2 is shown in Table 17-46.

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Internal. Only to be used through TI provided API.

Table 17-46 TEST2 Register Field Descriptions
BitFieldTypeResetDescription
31CDAC_OVST_ENR/W0hInternal. Only to be used through TI provided API.
30-25RESERVEDR0hReserved
24LATCH_TRIM_ENR/W0hInternal. Only to be used through TI provided API.
23-21RESERVEDR0hReserved
20COMP_GAIN_TRIMR/W0hInternal. Only to be used through TI provided API.
19-9RESERVEDR0hReserved
8MUX_TEST_SELR/W0hInternal. Only to be used through TI provided API.
7-0RESERVEDR0hReserved

17.5.38 TEST3 Register (Offset = E0Ch) [Reset = 00000000h]

TEST3 is shown in Table 17-47.

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Internal. Only to be used through TI provided API.

Table 17-47 TEST3 Register Field Descriptions
BitFieldTypeResetDescription
31-0CAL_ACUMLR/W0hInternal. Only to be used through TI provided API.

17.5.39 TEST4 Register (Offset = E10h) [Reset = 00000000h]

TEST4 is shown in Table 17-48.

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Internal. Only to be used through TI provided API.

Table 17-48 TEST4 Register Field Descriptions
BitFieldTypeResetDescription
31HW_STEP_SEL_DISR/W0hInternal. Only to be used through TI provided API.
30-25RESERVEDR0hReserved
24CAL_MODE_ENR/W0hInternal. Only to be used through TI provided API.
23-22RESERVEDR0hReserved
21-16CAL_STEP_SELR/W0hInternal. Only to be used through TI provided API.
15-0RESERVEDR0hReserved

17.5.40 TEST5 Register (Offset = E14h) [Reset = 00000000h]

TEST5 is shown in Table 17-49.

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Internal. Only to be used through TI provided API.

Table 17-49 TEST5 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0hReserved
9-0CAL_CAP_CTLR/W0hInternal. Only to be used through TI provided API.

17.5.41 TEST6 Register (Offset = E18h) [Reset = 00000000h]

TEST6 is shown in Table 17-50.

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Internal. Only to be used through TI provided API.

Table 17-50 TEST6 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0ATESTSELR/W0hInternal. Only to be used through TI provided API.

17.5.42 DEBUG1 Register (Offset = E20h) [Reset = 00801000h]

DEBUG1 is shown in Table 17-51.

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Internal. Only to be used through TI provided API.

Table 17-51 DEBUG1 Register Field Descriptions
BitFieldTypeResetDescription
31-0CTRLR/W00801000hInternal. Only to be used through TI provided API.

17.5.43 DEBUG2 Register (Offset = E24h) [Reset = 00000000h]

DEBUG2 is shown in Table 17-52.

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Internal. Only to be used through TI provided API.

Table 17-52 DEBUG2 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0hReserved
29-28VTOI_CTRLR/W0hInternal. Only to be used through TI provided API.
27-25RESERVEDR0hReserved
24VTOI_TESTMODE_ENR/W0hInternal. Only to be used through TI provided API.
23-0RESERVEDR0hReserved

17.5.44 DEBUG3 Register (Offset = E28h) [Reset = 00000000h]

DEBUG3 is shown in Table 17-53.

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Internal. Only to be used through TI provided API.

Table 17-53 DEBUG3 Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5DEC1_DISR/W0hInternal. Only to be used through TI provided API.
4DEC0_DISR/W0hInternal. Only to be used through TI provided API.
3-1RESERVEDR0hReserved
0BOOST_ENZR/W0hInternal. Only to be used through TI provided API.

17.5.45 DEBUG4 Register (Offset = E2Ch) [Reset = 00000000h]

DEBUG4 is shown in Table 17-54.

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Internal. Only to be used through TI provided API.

Table 17-54 DEBUG4 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0ADC_CTRL0R/W0hInternal. Only to be used through TI provided API.