SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
The I2C controller module generates an interrupt when a transaction completes (either transmit or receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I2C controller interrupt, software must set the IM bit in the I2C Controller Interrupt Mask register, I2C.CIMR. When an interrupt condition is met, software must check the I2C.CSTAT[4] ARBLST and I2C.CSTAT[1] ERR bits to verify that an error did not occur during the last transaction, and to check that arbitration has not been lost. An error condition is asserted if the last transaction was not acknowledged by the target. If an error is not detected and the controller has not lost arbitration, the application can proceed with the transfer. The interrupt is cleared by setting the IC bit in the I2C Controller Interrupt Clear register (I2C:CICR) to 1.
If the application does not require the use of interrupts, the raw interrupt status is always visible through the I2C Controller Raw Interrupt Status register (I2C:CRIS).