SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
The ADC has a dedicated interface for communicating with the µDMA. This interface is useful to offload work from the CPU by using the µDMA to store ADC results to memory automatically.
The DMAEN bit in the CTL2 register is used to enable the µDMA for ADC data transfer. The DMAEN bit is cleared by ADC hardware when the µDMA “DONE" status signal is asserted. Software is expected to reenable the µDMA using DMAEN to arm the ADC to generate the next µDMA trigger.
The ADC also incorporates an optional first-in-first-out buffer to provide a way for ADC results to be stored for future use, such as transferring to memory by the µDMA. Either the CPU or the µDMA can be used to move data from the ADC regardless of whether the FIFO is enabled or disabled. The memory result flags in the RIS register of the third event publisher serve as the FIFO threshold and can be unmasked to generate the µDMA trigger.
The following sections explain the details of using the ADC with µDMA or CPU in various conversion modes and with the FIFO enabled or disabled.