SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5
Table 2-47 lists the memory-mapped registers for the SCB registers. All register offset addresses not listed in Table 2-47 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CPUID | CPUID Base Register | Go |
4h | ICSR | Interrupt Control State Register | Go |
8h | VTOR | Vector Table Offset Register | Go |
Ch | AIRCR | Application Interrupt and Reset Control Register | Go |
10h | SCR | System Control Register | Go |
14h | CCR | Configuration and Control Register | Go |
1Ch | SHPR2 | System Handler Priority Register 2 | Go |
20h | SHPR3 | System Handler Priority Register 3 | Go |
24h | SHCSR | System Handler Control and State Register | Go |
Complex bit access types are encoded to fit into small table cells. Table 2-48 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CPUID is shown in Table 2-49.
Return to the Summary Table.
CPUID Base Register
Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | IMPLEMENTER | R | 41h | Implementor code: 0x41 = ARM |
23-20 | VARIANT | R | 0h | Implementation defined variant number: 0x0 (for r0) |
19-16 | CONSTANT | R | Ch | Reads as 0xC |
15-4 | PARTNO | R | C60h | Number of processor within family: 0xC20 |
3-0 | REVISION | R | 1h | Implementation defined revision number: 0x1 = processor p1 revision. |
ICSR is shown in Table 2-50.
Return to the Summary Table.
Interrupt Control State Register
Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NMIPENDSET | R/W | 0h | Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not). 0x0:No effect 0x1:Set pending nmi |
30-29 | RESERVED | R | 0h | Reserved |
28 | PENDSVSET | R/W | 0h | Set pending PendSV bit. On reads this bit returns the pending state of PendSV 0x0:No effect 0x1:Set pending pendsv |
27 | PENDSVCLR | W | 0h | Clear pending PendSV bit 0x0:No effect 0x1:Clear pending pendsv |
26 | PENDSTSET | R/W | 0h | Set a pending SysTick bit. On reads this bit returns the pending state of SysTick. 0x0:No effect 0x1:Set pending systick |
25 | PENDSTCLR | W | 0h | Clear pending SysTick bit 0x0:No effect 0x1:Clear pending systick |
24 | RESERVED | R | 0h | Reserved |
23 | ISRPREEMPT | R | 0h | The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 0x0:A pending exception is not serviced. 0x1:A pending exception is serviced on exit from the debug halt state |
22 | ISRPENDING | R | 0h | External interrupt pending flag 0x0:Interrupt not pending 0x1:Interrupt pending |
21 | RESERVED | R | 0h | Reserved |
20-12 | VECTPENDING | R | 0h | Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. |
11-9 | RESERVED | R | 0h | Reserved |
8-0 | VECTACTIVE | R | 0h | Active exception number field. Reset clears the VECTACTIVE field. |
VTOR is shown in Table 2-51.
Return to the Summary Table.
Vector Table Offset Register
The VTOR holds the vector table offset address.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | TBLOFF | R/W | 0h | Bits [31:8] of the indicate the vector table offset address. |
7-0 | RESERVED | R | 0h | Reserved |
AIRCR is shown in Table 2-52.
Return to the Summary Table.
Application Interrupt and Reset Control Register
Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | VECTKEY | W | FA05h | Register key. To write to other parts of this register, you must ensure 0x5FA is written into the VECTKEY field. |
15 | ENDIANESS | R | 1h | Data endianness bit. The read value depends on the endian configuration implemented 0x0:Little endian 0x1:Be-8 big-endian |
14-3 | RESERVED | R | 0h | Reserved |
2 | SYSRESETREQ | W | 0h | Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. |
1 | VECTCLRACTIVE | W | 0h | Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. |
0 | RESERVED | R | 0h | Reserved |
SCR is shown in Table 2-53.
Return to the Summary Table.
System Control Register
System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | SEVONPEND | R/W | 0h | When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE. |
3 | RESERVED | R | 0h | Reserved |
2 | SLEEPDEEP | R/W | 0h | Sleep deep bit.
0h = not OK to turn off system clock 1h = indicates to the system that Cortex-M0 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. |
1 | SLEEPONEXIT | R/W | 0h | Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.
0h = Do not sleep when returning to thread mode 1h = Sleep on return to thread mode |
0 | RESERVED | R | 0h | Reserved |
CCR is shown in Table 2-54.
Return to the Summary Table.
Configuration and Control Register
The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | STKALIGN | R | 1h | Always set to 1. On exception entry, all exceptions are entered with 8-byte stack alignment and the context to restore it is saved. The SP is restored on the associated exception return. |
8-4 | RESERVED | R | 0h | Reserved |
3 | UNALIGN_TRP | R | 1h | Indicates that all unaligned accesses results in a Hard Fault. Trap for unaligned access is fixed at 1. |
2-0 | RESERVED | R | 0h | Reserved |
SHPR2 is shown in Table 2-55.
Return to the Summary Table.
System Handler Priority Register 2
System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | PRI_11 | R/W | 0h | Priority of system handler 11, SVCall |
29-0 | RESERVED | R | 0h | Reserved |
SHPR3 is shown in Table 2-56.
Return to the Summary Table.
System Handler Priority Register 3
System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | PRI_15 | R/W | 0h | Priority of system handler 15, SysTick |
29-24 | RESERVED | R | 0h | Reserved |
23-22 | PRI_14 | R/W | 0h | Priority of system handler 14, PendSV |
21-0 | RESERVED | R | 0h | Reserved |
SHCSR is shown in Table 2-57.
Return to the Summary Table.
System Handler Control and State Register
Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | SVCALLPENDED | R/W | 0h | Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. |
14-0 | RESERVED | R | 0h | Reserved |