SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 11-1 lists the memory-mapped registers for the SYSTIM registers. All register offset addresses not listed in Table 11-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Module Description | Go |
44h | IMASK | Interrupt mask | Go |
48h | RIS | Raw interrupt status | Go |
4Ch | MIS | Masked interrupt status | Go |
50h | ISET | Interrupt set | Go |
54h | ICLR | Interrupt clear | Go |
58h | IMSET | Interrupt mask set | Go |
5Ch | IMCLR | Interrupt mask clear | Go |
60h | EMU | Emulation | Go |
100h | TIME250N | Systime Count Value [31:0] | Go |
104h | TIME1U | Systime Count Value [33:2] | Go |
108h | OUT | channel's Ouput Value | Go |
10Ch | CH0CFG | channel0 Configuration. | Go |
110h | CH1CFG | channel1 Configuration. | Go |
114h | CH2CFG | channel2 Configuration. | Go |
118h | CH3CFG | channel3 Configuration. | Go |
11Ch | CH4CFG | channel4 Configuration. | Go |
120h | CH0CC | Channel 0 Capture/Compare Value | Go |
124h | CH1CC | Channel 1 Capture/Compare Value | Go |
128h | CH2CC | Channel 2 Capture/Compare Value | Go |
12Ch | CH3CC | Channel 3 Capture/Compare Value | Go |
130h | CH4CC | Channel 4 Capture/Compare Value | Go |
134h | TIMEBIT | Systimer's Time bit | Go |
140h | STATUS | Timer Status | Go |
144h | ARMSET | Channel arming set | Go |
148h | ARMCLR | Channel Arming clear | Go |
14Ch | CH0CCSR | Channel 0 Save/Restore Value | Go |
150h | CH1CCSR | Channel 1 Save/Restore Value | Go |
154h | CH2CCSR | Channel 2 Save/Restore Value | Go |
158h | CH3CCSR | Channel 3 Save/Restore Value | Go |
15Ch | CH4CCSR | Channel 4 Save/Restore Value | Go |
Complex bit access types are encoded to fit into small table cells. Table 11-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 11-3.
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Description.
This register identifies the peripheral and its exact version.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 9443h | Module identifier used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 1h | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
11-8 | INSTIDX | R | 0h | IP Instance ID number. If multiple instances of IP exists in SOC, this field can identify the instance number 0-15 |
7-4 | MAJREV | R | 1h | Major revision of IP 0-15 |
3-0 | MINREV | R | 0h | Minor revision of IP 0-15. |
IMASK is shown in Table 11-4.
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Interrupt mask.
This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | R/W | 0h | Systimer counter overflow event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
4 | EV4 | R/W | 0h | Systimer channel 4 event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
3 | EV3 | R/W | 0h | Systimer channel 3 event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
2 | EV2 | R/W | 0h | Systimer channel 2 event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
1 | EV1 | R/W | 0h | Systimer channel 1 event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
0 | EV0 | R/W | 0h | Systimer channel 0 event interrupt mask.
0h = Disable Interrupt Mask 1h = Enable Interrrupt Mask |
RIS is shown in Table 11-5.
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Raw interrupt status.
This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | R | 0h | Raw interrupt status for Systimer counter overflow event. This bit is set to 1 when an event is received on SysTimer Overflow occurs. 0h = Interrupt did not occur 1h = Interrupt occured |
4 | EV4 | R | 0h | Raw interrupt status for channel 4 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 4. 0h = Interrupt did not occur 1h = Interrupt occured |
3 | EV3 | R | 0h | Raw interrupt status for channel 3 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 3. 0h = Interrupt did not occur 1h = Interrupt occured |
2 | EV2 | R | 0h | Raw interrupt status for channel 2 Event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 2. 0h = Interrupt did not occur 1h = Interrupt occured |
1 | EV1 | R | 0h | Raw interrupt status for channel 1 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 1. 0h = Interrupt did not occur 1h = Interrupt occured |
0 | EV0 | R | 0h | Raw interrupt status for channel 0 event. This bit is set to 1 when a CAPTURE or COMPARE event is received on channel 0. 0h = Interrupt did not occur 1h = Interrupt occured |
MIS is shown in Table 11-6.
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Masked interrupt status.
This register is simply a bitwise AND of the contents of IMASK and RIS.*] registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | R | 0h | Mask Interrupt status for Systimer counter overflow Event in MIS register.
0h = Interrupt did not occur 1h = Interrupt occured |
4 | EV4 | R | 0h | Mask interrupt status for channel 4 event.
0h = Interrupt did not occur 1h = Interrupt occured |
3 | EV3 | R | 0h | Mask interrupt status for channel 3 event.
0h = Interrupt did not occur 1h = Interrupt occured |
2 | EV2 | R | 0h | Mask interrupt status for channel 2 event.
0h = Interrupt did not occur 1h = Interrupt occured |
1 | EV1 | R | 0h | Mask interrupt status for channel 1 event.
0h = Interrupt did not occur 1h = Interrupt occured |
0 | EV0 | R | 0h | Mask interrupt status for channel 0 event.
0h = Interrupt did not occur 1h = Interrupt occured |
ISET is shown in Table 11-7.
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Interrupt set.
This register can used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | W | 0h | Sets Systimer counter overflow interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
4 | EV4 | W | 0h | Sets channel 4 interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
3 | EV3 | W | 0h | Sets channel 3 interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
2 | EV2 | W | 0h | Sets channel 2 interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
1 | EV1 | W | 0h | Sets channel 1 interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
0 | EV0 | W | 0h | Sets channel 0 interrupt.
0h = Writing 0 has no effect 1h = Set Interrupt |
ICLR is shown in Table 11-8.
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Interrupt clear.
'This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | W | 0h | Clears Systimer counter overflow interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
4 | EV4 | W | 0h | Clears channel 4 interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
3 | EV3 | W | 0h | Clears channel 3 interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
2 | EV2 | W | 0h | Clears channel 2 interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
1 | EV1 | W | 0h | Clears channel 1 interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
0 | EV0 | W | 0h | Clears channel 0 interrupt.
0h = Writing 0 has no effect 1h = Clear Interrupt |
IMSET is shown in Table 11-9.
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Interrupt mask set.
Writing a 1 to a bit in this register will set the corresponding IMASK bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | W | 0h | Sets Timer Overflow Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Set interrupt mask |
4 | EV4 | W | 0h | Sets channel4 Event Interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
3 | EV3 | W | 0h | Sets channel3 Event Interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
2 | EV2 | W | 0h | Sets channel2 Event Interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
1 | EV1 | W | 0h | Sets channel1 Event Interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
0 | EV0 | W | 0h | Sets channel0 Event Interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
IMCLR is shown in Table 11-10.
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Interrupt mask clear.
Writing a 1 to a bit in this register will clear the corresponding IMASK bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved |
5 | OVFL | W | 0h | Clears Timer Overflow Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
4 | EV4 | W | 0h | Clears channel4 Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
3 | EV3 | W | 0h | Clears channel3 Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
2 | EV2 | W | 0h | Clears channel2 Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
1 | EV1 | W | 0h | Clears channel1 Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
0 | EV0 | W | 0h | Clears channel0 Event Interrupt Mask.
0h = Writing 0 has no effect 1h = Clear interrupt mask |
EMU is shown in Table 11-11.
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Emulation control.
This register controls the behavior of the IP related to core halted input.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | HALT | R/W | 0h | Halt control.
0h = Free run option. The IP ignores the state of the core halted input. 1h = Freeze option. The IP freezes functionality when the core halted input is asserted, and resumes when it is deasserted. The freeze can either be immediate or after the IP has reached a boundary from where it can resume without corruption. |
TIME250N is shown in Table 11-12.
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Systimer Counter Value - 250ns resolution.
This 32-bit value reads out bits [31:0] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 250ns with a range of about 17.9m.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | 32-bit counter value [31:0]. This will provide a 250ns resolution and a range of 17.9m. |
TIME1U is shown in Table 11-13.
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Systimer Counter Value - 1μs resolution
This 32-bit value reads out bits[33:2] of the systimer counter. The counter is 34-bit and runs on CLKSVT/12. It maintains a resolution of 1us with a range of about 1 h 11m.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | 32-bit counter value [33:2]. This will provide a resolution of 1us and a range of 1hr and 11m. |
OUT is shown in Table 11-14.
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Systimer's channel Output Event Values
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | OUT4 | R/W | 0h | Output Value of channel 4.
0h = Event did not occur. 1h = Event occured |
3 | OUT3 | R/W | 0h | Output Value of channel 3.
0h = Event did not occur. 1h = Event occured |
2 | OUT2 | R/W | 0h | Output Value of channel 2.
0h = Event did not occur. 1h = Event occured |
1 | OUT1 | R/W | 0h | Output Value of channel 1.
0h = Event did not occur. 1h = Event occured |
0 | OUT0 | R/W | 0h | Output Value of channel 0.
0h = Event did not occur. 1h = Event occured |
CH0CFG is shown in Table 11-15.
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Systimer channel 0 configuration.
This channel has configurability for 250ns and 1us based capture and compare operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | RES | R/W | 0h | This bit decides the RESOLUTION of the channel that will be used.
0h = channel Works in Timer's 1us Resolution. 1h = channel Works in Timer's 250ns resolution |
3 | REARM | R/W | 0h | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled 1h = Re arm is enabled |
2-1 | INP | R/W | 0h | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function.
0h = Capture on rising edge 1h = Capture on Falling Edge 2h = Capture on both Edge |
0 | MODE | R/W | 0h | Decides the channel mode.
0h = channel is disabled 1h = channel is in capture mode |
CH1CFG is shown in Table 11-16.
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Systimer channel 1 configuration.
This channel works in 1us based capture and compare operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | REARM | R/W | 0h | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled 1h = Re arm is enabled |
2-1 | INP | R/W | 0h | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge 1h = Capture on Falling Edge 2h = Capture on both Edge |
0 | MODE | R/W | 0h | Decides the channel mode.
0h = channel is disabled 1h = channel is in capture mode |
CH2CFG is shown in Table 11-17.
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Systimer channel 2 configuration.
This channel works in 250ns based capture and compare operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | REARM | R/W | 0h | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled 1h = Re arm is enabled |
2-1 | INP | R/W | 0h | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge 1h = Capture on Falling Edge 2h = Capture on both Edge |
0 | MODE | R/W | 0h | Decides the channel mode.
0h = channel is disabled 1h = channel is in capture mode |
CH3CFG is shown in Table 11-18.
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Systimer channel 3 configuration.
This channel works in 250ns based capture and compare operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | REARM | R/W | 0h | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled 1h = Re arm is enabled |
2-1 | INP | R/W | 0h | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge 1h = Capture on Falling Edge 2h = Capture on both Edge |
0 | MODE | R/W | 0h | Decides the channel mode.
0h = channel is disabled 1h = channel is in capture mode |
CH4CFG is shown in Table 11-19.
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Systimer channel 4 configuration.
This channel works in 250ns based capture and compare operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | REARM | R/W | 0h | When Rearm is enabled the channel remains in continous capture mode. Otherwise it'll be in one shot capture mode. Rearm is only valid for capture mode.
0h = Re Arm is disabled 1h = Re arm is enabled |
2-1 | INP | R/W | 0h | Decides the channel input signal's mode. Setting the Value as 2'b11 selects the Rise Function
0h = Capture on rising edge 1h = Capture on Falling Edge 2h = Capture on both Edge |
0 | MODE | R/W | 0h | Decides the channel mode.
0h = channel is disabled 1h = channel is in capture mode |
CH0CC is shown in Table 11-20.
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System Timer channel 0 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH1CC is shown in Table 11-21.
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System Timer channel 1 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH2CC is shown in Table 11-22.
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System Timer channel 2 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH3CC is shown in Table 11-23.
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System Timer channel 3 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH4CC is shown in Table 11-24.
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System Timer channel 4 Capture/Compare register.
This register when written with any compare value will arm the channel to work in compare mode.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
TIMEBIT is shown in Table 11-25.
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Systimer's Time bit.
This Register will be used to specify which TIME bit is required by LGPT to be forwarded from SYSTIMER.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VAL | R/W | 0h | The corresponding bit will have value '1' rest should be '0'. If more than one bit is asserted, output is "or" of all the bits.
0h = No bit is forwarded to the event fabric. 1h = Bit2 is forwarded to the event fabric. 2h = Bit3 is forwarded to the event fabric. 4h = Bit4 is forwarded to the event fabric. 8h = Bit5 is forwarded to the event fabric. 10h = Bit6 is forwarded to the event fabric. 20h = Bit7 is forwarded to the event fabric. 40h = Bit8 is forwarded to the event fabric. 80h = Bit9 is forwarded to the event fabric. 100h = Bit10 is forwarded to the event fabric. 200h = Bit11 is forwarded to the event fabric. 400h = Bit12 is forwarded to the event fabric. 800h = Bit13 is forwarded to the event fabric. 1000h = Bit14 is forwarded to the event fabric. 2000h = Bit15 is forwarded to the event fabric. 4000h = Bit16 is forwarded to the event fabric. 8000h = Bit17 is forwarded to the event fabric. |
STATUS is shown in Table 11-26.
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Systimer status.
This register can be used to read the running status of the timer and to resync the Systimer with RTC.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | SYNCUP | R/W | 1h | This bit indicates sync status of Systimer with RTC. The bitfield has a reset value of '1', which gets cleared to '0' after the Systimer synchronizes with RTC on the first LFTICK edge. A write to this bit resynchronizes the Systimer with RTC on the next LFTICK edge. A read value of '1' indicates the synchronization is ongoing and a read of '0' indicates the synchronization is done. |
3-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R | 0h | This bit indicates if the system time is initialized and running.
0h = system timer is not running. 1h = system timer is running |
ARMSET is shown in Table 11-27.
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ARMSET
Reading this register gives out the status of the 5 channels.
Channel state UNARMED returns 0.
Channel state CAPTURE or COMPARE returns 1.
A write to ARMSET has for each channel the following effect -
If ARMSTA[x]==0 -> no effect
If ARMSTA[x]==1 and channel x is in CAPTURE state then no effect on the channel
Else, set channel in COMPARE mode using existing CHxVAL value
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | CH4 | R/W | 0h | Arming channel 4 for either compare or capture operation.
0h = No effect on the channel 1h = if channel 4 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH4CC.VAL value. |
3 | CH3 | R/W | 0h | Arming channel 3 for either compare or capture operation.
0h = No effect on the channel 1h = if channel 3 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH3CC.VAL value |
2 | CH2 | R/W | 0h | Arming channel 2 for either compare or capture operation.
0h = No effect on the channel 1h = if channel 2 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH2CC.VAL value |
1 | CH1 | R/W | 0h | Arming channel 1 for either compare or capture operation.
0h = No effect on the channel 1h = if channel 1 is in CAPTURE state then no effect on the channel else it can Set channel in COMPARE mode using existing CH1CC.VAL value |
0 | CH0 | R/W | 0h | Arming channel 0 for either compare or capture operation.
0h = No effect on the channel 1h = if channel 0 is in CAPTURE state then no effect on the channel else it can set channel in COMPARE mode using existing CH0CC.VAL value |
ARMCLR is shown in Table 11-28.
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ARMCLR
Read of this register gives out the status of the 5 channels .
Channel state UNARMED returns 0.
Channel state CAPTURE or COMPARE returns 1.
A write to ARMCLR has for each channel the following effect -
If ARMCLR[x]==0 -> no effect.
Else, set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | CH4 | R/W | 0h | Disarming channel 4
0h = No effect on the channel 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
3 | CH3 | R/W | 0h | Disarming channel 3
0h = No effect on the channel 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
2 | CH2 | R/W | 0h | Disarming channel 2
0h = No effect on the channel 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
1 | CH1 | R/W | 0h | Disarming channel 1
0h = No effect on the channel 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
0 | CH0 | R/W | 0h | Disarming channel 0
0h = No effect on the channel 1h = Set channel in UNARMED state without triggering event unless a compare/capture event happens in the same cycle |
CH0CCSR is shown in Table 11-29.
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Save/restore alias register for channel 0.
A read to this register behaves exactly as a read to CH0CC.
Write to CH0CCSR sets CH0CC.VAL value of register without affecting channel state or configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH1CCSR is shown in Table 11-30.
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Save/restore alias registers channel 1.
A read to CH1CCSR behaves exactly as a read to CH1VAL.
Write to this register sets CH1CC.VAL without affecting channel state or configuration.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH2CCSR is shown in Table 11-31.
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Save/restore alias registers channel 2.
A read to CH2CCSR behaves exactly as a read to CH2CC
Write to CH2CCSR sets CH2CC.VAL value of register without affecting channel state or configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH3CCSR is shown in Table 11-32.
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Save/restore alias registers channel 3.
A read to CH3CCSR behaves exactly as a read to CH3CC
Write to CH3CCSR sets CH3CC.VAL value of register without affecting channel state or configuration.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |
CH4CCSR is shown in Table 11-33.
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Save/restore alias registers channel 4.
A read to CH4CCSR behaves exactly as a read to CH4CC
Write to CH4CCSR sets CH4CC.VAL value of register without affecting channel state or configuration.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Capture/compare value |