SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 16-1 lists the memory-mapped registers for the AES registers. All register offset addresses not listed in Table 16-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Description Register. | Go |
10h | TRG | Trigger | Go |
14h | ABORT | Abort | Go |
18h | CLR | Clear | Go |
1Ch | STA | Status | Go |
20h | DMA | Direct Memory Access | Go |
24h | DMACHA | DMA Channel A data transfer | Go |
28h | DMACHB | DMA Channel B data transfer | Go |
2Ch | AUTOCFG | Automatic Configuration | Go |
50h | KEY0 | Key Word 0 | Go |
54h | KEY1 | Key Word 1 | Go |
58h | KEY2 | Key Word 2 | Go |
5Ch | KEY3 | Key Word 3 | Go |
70h | TXT0 | Text Word 0 | Go |
74h | TXT1 | Text Word 1 | Go |
78h | TXT2 | Text Word 2 | Go |
7Ch | TXT3 | Text Word 3 | Go |
80h | TXTX0 | Text Word 0 XOR | Go |
84h | TXTX1 | Text Word 1 XOR | Go |
88h | TXTX2 | Text Word 2 XOR | Go |
8Ch | TXTX3 | Text Word 3 XOR | Go |
90h | BUF0 | Buffer Word 0 | Go |
94h | BUF1 | Buffer Word 1 | Go |
98h | BUF2 | Buffer Word 2 | Go |
9Ch | BUF3 | Buffer Word 3 | Go |
A0h | TXTXBUF0 | Text Word 0 XOR Buffer Word 0 | Go |
A4h | TXTXBUF1 | Text Word 1 XOR Buffer Word 1 | Go |
A8h | TXTXBUF2 | Text Word 2 XOR Buffer Word 2 | Go |
ACh | TXTXBUF3 | Text Word 3 XOR Buffer Word3 | Go |
104h | IMASK | Interrupt Mask register | Go |
108h | RIS | Raw Interrupt Status register | Go |
10Ch | MIS | Masked Interrupt Status register | Go |
110h | ISET | Interrupt Set register | Go |
114h | ICLR | Interrupt Clear register | Go |
118h | IMSET | Interrupt Mask Set register | Go |
11Ch | IMCLR | Interrupt Mask Clear register | Go |
Complex bit access types are encoded to fit into small table cells. Table 16-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | R H | Read Set or cleared by hardware |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 16-3.
Return to the Summary Table.
Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 6B42h | Module Identifier This register is used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 4h | Standard IP MMR block offset Standard IP MMRs are the set from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist. 0x1-0xF: Standard IP MMRs begin at offset of 64*STDIPOFF from the base IP address. |
11-8 | INSTIDX | R | 0h | IP Instance ID number If multiple instances of IP exist in the device, this field can identify the instance number (0-15). |
7-4 | MAJREV | R | 1h | Major revision of IP (0-15) |
3-0 | MINREV | R | 0h | Minor Revision of IP(0-15) |
TRG is shown in Table 16-4.
Return to the Summary Table.
Trigger
This register is used to manually trigger operations.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | DMACHA | W | 0h | Manually trigger channel A request
0h = Writing 0 has no effect 1h = Triggers channel A request |
2 | DMACHB | W | 0h | Manually trigger channel B request
0h = Writing 0 has no effect 1h = Triggers channel B request |
1-0 | AESOP | W | 0h | AES Operation Write an enumerated value to this field when STA.STATE = IDLE to manually trigger an AES operation. If condition is not met, the trigger is ignored. Non-enumerated values are ignored. Enumerated value indicates source of AES operation 1h = TXT = AES(KEY,TXT) 2h = TXT = AES(KEY,BUF) 3h = TXT = AES(KEY, TXT XOR BUF) |
ABORT is shown in Table 16-5.
Return to the Summary Table.
Abort
This register is used to abort current AES operation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ABORTAES | W | 0h | Abort AES operation Abort an ongoing AES operation. An abort will clear TXT, BUF, DMA, AUTOCFG registers 0h = Writing 0 has no effect 1h = Aborts an ongoing AES operation |
CLR is shown in Table 16-6.
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Clear
This register is used to clear contents of TXT and BUF when STA.STATE = IDLE. If condition is not met, the contents remain unchanged.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TXT | W | 0h | Clear TXT
0h = Writing 0 has no effect 1h = Clears TXT |
0 | BUF | W | 0h | Clear BUF
0h = Writing 0 has no effect 1h = Clears BUF |
STA is shown in Table 16-7.
Return to the Summary Table.
Status
This register provides information on AES accellerator state and BUF status.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | BUFSTA | R | 0h | BUF Status Field gives the status of BUF, indicating EMPTY or FULL, when AUTOCFG.TRGAES = WRBUF3. If AUTOCFG.TRGAES != WRBUF3, then STA.BUFSTA will hold the value 0. Note : Useful for CBC-MAC 0h = Data stored in BUF is already consumed by the AES engine and next block of data can be written in BUF. 1h = Data stored in BUF is not yet consumed by the AES engine. Next block of data cannot be written into BUF until STA.STATE = IDLE. |
0 | STATE | R | 0h | State Field gives the state of the AES engine. 0h = AES engine is IDLE 1h = AES operation active |
DMA is shown in Table 16-8.
Return to the Summary Table.
Direct Memory Access
This register controls the conditions that will generate burst requests on each DMA channel.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | DONEACT | R/W | 0h | Done Action This field determines the side effects of DMA done. It is allowed to configure this field with an OR-combination of supported enums, with the exception that GATE_TRGAES_ON_CHA and GATE_TRGAES_ON_CHA_DEL must be mutually exclusive 0h = DMA done has no side effect 1h = Triggers defined in AUTOCFG.TRGAES are gated when RIS.CHADONE = SET 2h = Delayed gating of triggers defined in AUTOCFG.TRGAES Due to the pipelining of BUF writes, in certain modes, DMA CHA Done appears before the last but one AES operation has completed. Setting this bit, will gate the triggers defined in AUTOCFG.TRGAES only after the last write by CHA is consumed by AES FSM. Used in ECB,CBC,CBC-MAC modes (having multiple blocks encryption/decryption) to avoid spurious AES operation triggered on last read by CHB. For single mode operation, DMA.GATE_TRGAES_ON_CHA must be used. 4h = DMA channel A done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met. 8h = DMA channel B done event clears TXT0 thru TXT3 if STA.STATE = IDLE. Event is ignored if condition is not met. |
15-14 | RESERVED | R | 0h | Reserved |
13-12 | ADRCHB | R/W | 0h | Channel B Read Write Address The DMA accesses DMACHB to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration. 0h = Start address is TXT0 1h = Start address is TXTX0 2h = Start address is BUF0 3h = Start address is TXTXBUF0 |
11 | RESERVED | R | 0h | Reserved |
10-8 | TRGCHB | R/W | 0h | Channel B Trigger Select the condition that triggers DMA channel B request. Non-enumerated values are not supported and ignored. 0h = DMA requests are disabled 1h = Start of AES operation triggers request 2h = Completion of AES operation triggers request 3h = Writes to TXT3, TXTX3, or TXTXBUF3 trigger request 4h = Reads of TXT3, or TXTXBUF3 trigger request |
7-6 | RESERVED | R | 0h | Reserved |
5-4 | ADRCHA | R/W | 0h | Channel A Read Write Address The DMA accesses DMACHA to read or write contents of TXT and BUF as a response to a burst request. This field specifes the start address of the first DMA transfer that follows the burst request. The internal address gets incremented automatically for subsequent accesses. The DMA can transfer 8-bit, 16-bit, or 32-bit words, and must always complete a 16-byte transfer before re-arbitration. 0h = Start address is TXT0 1h = Start address is TXTX0 2h = Start address is BUF0 3h = Start address is TXTXBUF0 |
3 | RESERVED | R | 0h | Reserved |
2-0 | TRGCHA | R/W | 0h | Channel A Trigger Select the condition that triggers DMA channel A request. Non-enumerated values are not supported and ignored. 0h = DMA requests are disabled 1h = Start of AES operation triggers request 2h = Completion of AES operation triggers request 3h = Writes to TXT3 or TXTX3 trigger request 4h = Reads of TXT3 or TXTXBUF3 trigger request |
DMACHA is shown in Table 16-9.
Return to the Summary Table.
DMA Channel A data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHA.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Value transferred through DMA Channel A |
DMACHB is shown in Table 16-10.
Return to the Summary Table.
DMA Channel B data transfer
DMA accesses this register to read or write contents from sequential addresses specifed by DMA.ADRCHB.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R/W | 0h | Value transferred through DMA Channel B |
AUTOCFG is shown in Table 16-11.
Return to the Summary Table.
Automatic Configuration
This register configures automatic hardware updates to TXT and BUF. Configure this register to reduce software overhead during cipher modes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R | 0h | Reserved |
28 | CHBDNCLR | R/W | 0h | This field enable auto-clear of RIS.CHBDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 . 0h = Disable auto-clear of RIS.CHBDONE interrupt 1h = Enable auto-clear of RIS.CHBDONE interrupt |
27 | CHADNCLR | R/W | 0h | This field enables auto-clear of RIS.CHADONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 . 0h = Disable auto-clear of RIS.CHADONE interrupt 1h = Enable auto-clear of RIS.CHADONE interrupt |
26 | CLRAESST | R/W | 0h | Clear AES Start This field enables auto-clear of RIS.AESSTART interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 . 0h = Disable auto-clear of RIS.AESSTART interrupt 1h = Enable auto-clear of RIS.AESSTART interrupt |
25 | CLRAESDN | R/W | 0h | Clear AES Done This field enables auto-clear of RIS.AESDONE interrupt on read/write of TXT3/BUF3/TXTX3/TXTXBUF3 . 0h = Disable auto-clear of RIS.AESDONE interrupt 1h = Enable auto-clear of RIS.AESDONE interrupt |
24 | BUSHALT | R/W | 0h | Bus Halt This field decides if bus halts on access to KEY, TXT, BUF, TXTX and TXTXBUF when STA.STATE = BUSY. 0h = Disable bus halt When STA.STATE = BUSY, writes to KEY, TXT, TXTX are ignored, reads from TXT, TXTXBUF return zero. When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, writes to BUF are ignored, reads return zero. 1h = Enable bus halt When STA.STATE = BUSY, access to KEY, TXT, TXTX, TXTXBUF halt the bus until STA.STATE = IDLE. When STA.STATE = BUSY and if either STA.BUFSTA = FULL or AUTOCFG.CTRSIZE != DISABLE, access to BUF halts the bus until STA.STATE = IDLE. |
23-22 | RESERVED | R | 0h | Reserved |
21-19 | CTRSIZE | R/W | 0h | Counter Size Configures size of counter as either 8,16,32,64 or 128 Non-enumerated values are not supported and ignored 0h = Disable CTR operation 1h = Configures counter size as 8-bit 2h = Configures counter size as 16-bit 3h = Configures counter size as 32-bit 4h = Configures counter size as 64-bit 5h = Configures counter size as 128-bit |
18 | CTRALIGN | R/W | 0h | Counter Alignment Specifies alignment of counter 0h = Indicates Left Aligned Counter Not applicable for 128-bit counter size. For 128-bit counter, all octets will be considered When left aligned,,octet 0-7 will be considered , based on counter size and endianness 1h = Indicates right aligned counter Not applicable when counter size is 128-bit For 128-bit counter, all octets will be considered If right aligned, octet 8-15 will be considered based on endianness and counter size |
17 | CTRENDN | R/W | 0h | Counter Endianness Specifies Endianness of counter 0h = Specifies Little Endian Counter Carry will flow from octet 'n' to octet 'n+1' 1h = Specifies Big Endian Counter Carry will flow from octet 'n' to octet 'n-1' |
16-10 | RESERVED | R | 0h | Reserved |
9-8 | TRGTXT | R/W | 0h | Trigger for TXT This field determines if and when hardware automatically XORs BUF into TXT. Non-enumerated values are not supported and ignored. It is allowed to configure this field with an OR-combination of supported enums. 0h = No hardware update of TXT 1h = Hardware XORs content of BUF into TXT upon read of TXT3 2h = Hardware XORs content of BUF into TXT upon read of TXTXBUF3 |
7-6 | RESERVED | R | 0h | Reserved |
5-4 | AESSRC | R/W | 0h | AES Source This field specifies the data source to hardware-triggered AES operations. Non-enumerated values are not supported and ignored. 1h = TXT = AES(KEY,TXT) 2h = TXT = AES(KEY,BUF) 3h = TXT = AES(KEY, TXT XOR BUF) |
3-0 | TRGAES | RH/W | 0h | Trigger Electronic Codebook This field specifies one or more actions that indirectly trigger AES operation. It is allowed to configure this field with an OR-combination of supported enums. 0h = No user action indirectly triggers AES operation 1h = All writes to TXT3 or TXTX3 trigger action, only when STA.STATE = IDLE 2h = All reads of TXT3 or TXTXBUF3 trigger action, only when STA.STATE = IDLE 4h = All writes to BUF3 will schedule to trigger action once STA.STATE is or becomes IDLE, only when AUTOCFG.CTRSIZE = DIS 8h = Write to BUF3 will schedule to trigger single action once STA.STATE is or becomes IDLE. Subsequent writes do not trigger action unless this setting is written again to this field. |
KEY0 is shown in Table 16-12.
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Key Word 0
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value of KEY[31:0] |
KEY1 is shown in Table 16-13.
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Key Word 1
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value of KEY[63:32] |
KEY2 is shown in Table 16-14.
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Key Word 2
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value of KEY[95:64] |
KEY3 is shown in Table 16-15.
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Key Word 3
Write KEY0 through KEY3 to populate the 128-bit key. The key is not consumed by the hardware. It is hence not required to reload the key for subsequent block encryptions/decryptions unless required by the application.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value of KEY[127:96] |
TXT0 is shown in Table 16-16.
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Text Word 0
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of TXT[31:0] |
TXT1 is shown in Table 16-17.
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Text Word 1
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of TXT[63:32] |
TXT2 is shown in Table 16-18.
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Text Word 2
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of TXT[95:64] |
TXT3 is shown in Table 16-19.
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Text Word 3
TXT is the 128-bit buffer, the AES-128 algorithm performs its operations on. AES input can be written to TXT, and ciphertext can be read from TXT.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of TXT[127:96] AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation. |
TXTX0 is shown in Table 16-20.
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Text Word 0 XOR
Write data to this register to XOR data with contents in TXT0.VAL.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value in TXT0 will be TXT0.VAL = VAL XOR TXT0.VAL |
TXTX1 is shown in Table 16-21.
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Text Word 1 XOR
Write data to this register to XOR data with contents in TXT1.VAL.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value in TXT1 will be TXT1.VAL = VAL XOR TXT1.VAL |
TXTX2 is shown in Table 16-22.
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Text Word 2 XOR
Write data to this register to XOR data with contents in TXT2.VAL.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value in TXT2 will be TXT2.VAL = VAL XOR TXT2.VAL |
TXTX3 is shown in Table 16-23.
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Text Word 3 XOR
Write data to this register to XOR data with contents in TXT3.VAL.
AUTOCFG.TRGAES decides if a write to or a read of this field triggers an AES operation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | W | 0h | Value in TXT3 will be TXT3.VAL = VAL XOR TXT3.VAL |
BUF0 is shown in Table 16-24.
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Buffer Word 0
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of BUF[31:0] |
BUF1 is shown in Table 16-25.
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Buffer Word 1
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of BUF[63:32] |
BUF2 is shown in Table 16-26.
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Buffer Word 2
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of BUF[95:64] |
BUF3 is shown in Table 16-27.
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Buffer Word 3
BUF is a 128-bit auxiliary register that functions as a buffer, counter, or storage of operations in cipher modes.
AUTOCFG.TRGAES decides if a write to this field triggers an AES operation.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | RH/W | 0h | Value of BUF[127:96] |
TXTXBUF0 is shown in Table 16-28.
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Text Word 0 XOR Buffer Word 0
Read this register to obtain plaintext during CFB decryption.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | Value read will be TXT0.VAL XOR BUF0.VAL |
TXTXBUF1 is shown in Table 16-29.
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Text Word 1 XOR Buffer Word 1
Read this register to obtain plaintext during CFB decryption.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | Value read will be TXT1.VAL XOR BUF1.VAL |
TXTXBUF2 is shown in Table 16-30.
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Text Word 2 XOR Buffer Word 2
Read this register to obtain plaintext during CFB decryption.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | Value read will be TXT2.VAL XOR BUF2.VAL |
TXTXBUF3 is shown in Table 16-31.
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Text Word 3 XOR Buffer Word3
Read this register to obtain plaintext during CFB decryption.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | VAL | R | 0h | Value read will be TXT3.VAL XOR BUF3.VAL |
IMASK is shown in Table 16-32.
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Interrupt Mask register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | R/W | 0h | DMA Channel B Done interrupt mask
0h = Disable interrupt mask 1h = Enable interrupt mask |
2 | CHADONE | R/W | 0h | DMA Channel A Done interrupt mask
0h = Disable interrupt mask 1h = Enable interrupt mask |
1 | AESSTART | R/W | 0h | AES Start interrupt mask
0h = Disable interrupt mask 1h = Enable interrupt mask |
0 | AESDONE | R/W | 0h | AES Done interrupt mask
0h = Disable interrupt mask 1h = Enable interrupt mask |
RIS is shown in Table 16-33.
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Raw Interrupt Status register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | R | 0h | Raw Interrupt Status for DMA Channel B Done
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | CHADONE | R | 0h | Raw Interrupt Status for DMA Channel A Done
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | AESSTART | R | 0h | Raw Interrupt Status for AES Start
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | AESDONE | R | 0h | Raw Interrupt Status for AES Done
0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Table 16-34.
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Masked Interrupt Status register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | R | 0h | Masked Interrupt Status for DMA Channel B Done
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | CHADONE | R | 0h | Masked Interrupt Status for DMA Channel A Done
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | AESSTART | R | 0h | Masked Interrupt Status for AES Start
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | AESDONE | R | 0h | Masked Interrupt Status for AES Done
0h = Interrupt did not occur 1h = Interrupt occurred |
ISET is shown in Table 16-35.
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Interrupt Set register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | W | 0h | Set DMA Channel B Done interrupt
0h = Writing 0 has no effect 1h = Set interrupt |
2 | CHADONE | W | 0h | Set DMA Channel A Done interrupt
0h = Writing 0 has no effect 1h = Set interrupt |
1 | AESSTART | W | 0h | Set AES Start interrupt
0h = Writing 0 has no effect 1h = Set interrupt |
0 | AESDONE | W | 0h | Set AES Done interrupt
0h = Writing 0 has no effect 1h = Set interrupt |
ICLR is shown in Table 16-36.
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Interrupt Clear register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | W | 0h | Clear DMA Channel B Done interrupt
0h = Writing 0 has no effect 1h = Clear interrupt |
2 | CHADONE | W | 0h | Clear DMA Channel A Done interrupt
0h = Writing 0 has no effect 1h = Clear interrupt |
1 | AESSTART | W | 0h | Clear AES Start interrupt
0h = Writing 0 has no effect 1h = Clear interrupt |
0 | AESDONE | W | 0h | Clear AES Done interrupt
0h = Writing 0 has no effect 1h = Clear interrupt |
IMSET is shown in Table 16-37.
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Interrupt Mask Set register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | W | 0h | Set DMA Channel B Done interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
2 | CHADONE | W | 0h | Set DMA Channel A Done interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
1 | AESSTART | W | 0h | Set AES Start interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
0 | AESDONE | W | 0h | Set AES Done interrupt mask
0h = Writing 0 has no effect 1h = Set interrupt mask |
IMCLR is shown in Table 16-38.
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Interrupt Mask Clear register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CHBDONE | W | 0h | Clear DMA Channel B Done interrupt mask
0h = Writing 0 has no effect 1h = Clear interrupt mask |
2 | CHADONE | W | 0h | Clear DMA Channel A Done interrupt mask
0h = Writing 0 has no effect 1h = Clear interrupt mask |
1 | AESSTART | W | 0h | Clear AES Start interrupt mask
0h = Writing 0 has no effect 1h = Clear interrupt mask |
0 | AESDONE | W | 0h | Clear AES Done interrupt mask
0h = Writing 0 has no effect 1h = Clear interrupt mask |