SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 4-5 lists the memory-mapped registers for the EVTULL registers. All register offset addresses not listed in Table 4-5 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Description | Go |
4h | DESCEX | Extended Description | Go |
64h | DTB | Digital test bus control register | Go |
400h | NMISEL | Output Selection for CPU NMI Exception | Go |
404h | RTCCPTSEL | Output Selection for RTCCPT | Go |
800h | WKUPMASK | WAKEUP Mask | Go |
Complex bit access types are encoded to fit into small table cells. Table 4-6 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 4-7.
Return to the Summary Table.
Description
This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 3045h | Module identifier used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 1h | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
11-8 | INSTIDX | R | 0h | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). |
7-4 | MAJREV | R | 1h | Major revision of IP (0-15). |
3-0 | MINREV | R | 0h | Minor revision of IP (0-15). |
DESCEX is shown in Table 4-8.
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Extended Description
This register provides configuration details of the IP to software drivers and end users.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | IDMA | R | 0h | Number of DMA input channels |
21-17 | NDMA | R | 0h | Number of DMA output channels |
16 | PD | R | 1h | Power Domain. 0 : SVT 1 : ULL |
15-8 | NSUB | R | 1h | Number of Subscribers |
7-0 | NPUB | R | 6h | Number of Publishers |
DTB is shown in Table 4-9.
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Digital test bus control register
This register can be used to bring out IP internal signals to the pads for observation. 16 signals can be observed per select value.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
0 | SEL | R/W | 0h | Digital test bus selection mux control Non-zero select values output a 16 bit selected group of signals per value. |
NMISEL is shown in Table 4-10.
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Output Selection for CPU NMI Exception
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
5-0 | PUBID | R/W | 0h | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS 4h = AON_RTC event, controlled by the RTC:IMASK setting 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 7h = IOC synchronous combined event, controlled by IOC:EVTCFG |
RTCCPTSEL is shown in Table 4-11.
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Output Selection for RTCCPT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
5-0 | PUBID | R/W | 0h | Read/write selection value. Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 2h = PMU combined interrupt request for BATMON, interrupt flags can be found here PMUD:EVENT 3h = CKMD combined interrupt request, interrupt flags can be found here CKMD:MIS 4h = AON_RTC event, controlled by the RTC:IMASK setting 5h = DebugSS combined interrupt, interrupt flags can be found here DBGSS:MIS 6h = AON LPCMP interrupt, controlled by SYS0:LPCMPCFG 7h = IOC synchronous combined event, controlled by IOC:EVTCFG |
WKUPMASK is shown in Table 4-12.
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WAKEUP Mask
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
7 | AON_IOC_COMB | R/W | 0h | Wake-up mask for AON_IOC_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
6 | AON_LPMCMP_IRQ | R/W | 0h | Wake-up mask for AON_LPMCMP_IRQ. 0 - Wakeup Disabled 1 - Wakeup Enabled |
5 | AON_DBG_COMB | R/W | 0h | Wake-up mask for AON_DBG_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
4 | AON_RTC_COMB | R/W | 0h | Wake-up mask for AON_RTC_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
3 | AON_CKM_COMB | R/W | 0h | Wake-up mask for AON_CKM_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
2 | AON_PMU_COMB | R/W | 0h | Wake-up mask for AON_PMU_COMB. 0 - Wakeup Disabled 1 - Wakeup Enabled |
1-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |