SWCU193A April   2023  – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  3. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 Flash
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  4. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  5. 3 Memory Map
    1. 3.1 Memory Map
  6. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  7. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  8. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 Reset
      2. 6.4.2 Shutdown
      3. 6.4.3 Active
      4. 6.4.4 Idle
      5. 6.4.5 Standby
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  9. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 Flash
        1. 7.2.4.1 Flash Read-Only Protection
        2. 7.2.4.2 Flash Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  10. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
        5. 8.2.4.5 Debug Flow Charts
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  11. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  12. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Deadband
      6. 10.4.6 Deadband, Fault, and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  13. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  14. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  15. 13Low Power Comparator and SYS0
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-Up
    4. 13.4 SYS0 Registers
  16. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  17. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  18. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  19. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power-Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA and FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-Hoc Single Conversion
    5. 17.5 ADC Registers
  20. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  21. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  22. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  23. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  24. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-Domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers
  25. 23Revision History

5.10 DBGSS Registers

Table 5-7 lists the memory-mapped registers for the DBGSS registers. All register offset addresses not listed in Table 5-7 should be considered as reserved locations and the register contents should not be modified.

Table 5-7 DBGSS Registers
OffsetAcronymRegister NameSection
0hDESCModule DescriptionGo
44hIMASKInterrupt maskGo
4ChRISRaw interrupt statusGo
54hMISMasked interrupt statusGo
5ChISETInterrupt setGo
64hICLRInterrupt clearGo
6ChIMSETSet Interupt Mask in IMASKGo
74hIMCLRClear Interupt Mask in IMASKGo
100hTXDTransmit data registerGo
104hTXCTLTransmit control registerGo
108hRXDReceive data registerGo
10ChRXCTLReceive control registerGo
110hTXDPEEKTransmit Data Peek RegisterGo
114hRXDPEEKReceive Data Peek RegisterGo
200hSPECIAL_AUTHSpecial enable authorization registerGo
204hSPECIAL_AUTH_SETSpecial enable authorization set registerGo
208hSPECIAL_AUTH_CLRSpecial enable authorization clear registerGo
210hAPP_AUTHApplication authorization registerGo
214hAPP_AUTH_SETApplication authorization set registerGo
218hAPP_AUTH_CLRApplication authorization clear registerGo
21ChDBGCTLDebug control registerGo

Complex bit access types are encoded to fit into small table cells. Table 5-8 shows the codes that are used for access types in this section.

Table 5-8 DBGSS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

5.10.1 DESC Register (Offset = 0h) [Reset = B24D1010h]

DESC is shown in Table 5-9.

Return to the Summary Table.

Description Register. This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 5-9 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR/WB24DhModule identifier used to uniquely identify this IP.
0h = Minimum value
FFFFh = Maximum possible value
15-12STDIPOFFR/W1hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
0: STDIP MMRs do not exist
0x1-0xF: These MMRs begin at offset 64*STDIPOFF from IP base address
0h = Minimum Value
Fh = Maximum possible value
11-8INSTIDXR/W0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
0h = Minimum Value
Fh = Maximum possible value
7-4MAJREVR/W1hMajor revision of IP (0-15).
0h = Minimum Value
Fh = Maximum possible value
3-0MINREVR/W0hMinor revision of IP (0-15).
0h = Minimum Value
Fh = Maximum possible value

5.10.2 IMASK Register (Offset = 44h) [Reset = 00000000h]

IMASK is shown in Table 5-10.

Return to the Summary Table.

Interrupt mask. This register selects interrupt sources which are allowed to pass from RIS to MIS when the corresponding bit-fields are set to 1.

Table 5-10 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hPWRDWNIFG interrupt mask
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
2PWRUPIFGR/W0hPWRUPIFG interrupt mask
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
1RXIFGR/W0hRXIFG interrupt mask
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set
0TXIFGR/W0hTXIFG interrupt mask
0h = Disable Interrupt Mask
1h = Enable Interrupt Mask

5.10.3 RIS Register (Offset = 4Ch) [Reset = 00000000h]

RIS is shown in Table 5-11.

Return to the Summary Table.

Raw interrupt status. This register reflects the state of all pending interrupts, regardless of masking. This register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 5-11 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hRaw interrupt status for PWRDWNIFG
0h = PWRDWNIFG did not occur
1h = PWRDWNIFG occurred
2PWRUPIFGR/W0hRaw interrupt status for PWRUPIFG
0h = PWRUPIFG did not occur
1h = PWRUPIFG occurred
1RXIFGR/W0hRaw interrupt status for RXIFG
0h = RXIFG did not occur
1h = RXIFG occurred
0TXIFGR/W0hRaw interrupt status for TXIFG
0h = TXIFG did not occur
1h = TXIFG occurred

5.10.4 MIS Register (Offset = 54h) [Reset = 00000000h]

MIS is shown in Table 5-12.

Return to the Summary Table.

Masked interrupt status. This register is simply a bitwise AND of the contents of IMASK and RIS registers. A flag set in this register can be cleared by writing 1 to the corresponding ICLR register bit.

Table 5-12 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hMasked interrupt status for PWRDWNIFG
0h = PWRDWNIFG did not request an interrupt service routine
1h = PWRDWNIFG requests an interrupt service routine
2PWRUPIFGR/W0hMasked interrupt status for PWRUPIFG
0h = PWRUPIFG did not request an interrupt service routine
1h = PWRUPIFG requests an interrupt service routine
1RXIFGR/W0hMasked interrupt status for RXIFG
0h = RXIFG did not request an interrupt service routine
1h = RXIFG requests an interrupt service routine
0TXIFGR/W0hMasked interrupt status for TXIFG
0h = TXIFG did not request an interrupt service routine
1h = TXIFG requests an interrupt service routine

5.10.5 ISET Register (Offset = 5Ch) [Reset = 00000000h]

ISET is shown in Table 5-13.

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Interrupt set register. This register can be used by software for diagnostics and safety checking purposes. Writing a 1 to a bit in this register will set the event and the corresponding RIS bit also gets set. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets set.

Table 5-13 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hSets PWRDWNIFG in RIS register
0h = Writing a 0 has no effect
1h = Set interrupt
2PWRUPIFGR/W0hSets PWRUPIFG in RIS register
0h = Writing a 0 has no effect
1h = Set interrupt
1RXIFGR/W0hSets RXIFG in RIS register
0h = Writing a 0 has no effect
1h = Set interrupt
0TXIFGR/W0hSets TXIFG in RIS register
0h = Writing a 0 has no effect
1h = Set interrupt

5.10.6 ICLR Register (Offset = 64h) [Reset = 00000000h]

ICLR is shown in Table 5-14.

Return to the Summary Table.

Interrupt clear register. This register allows software to clear interrupts. Writing a 1 to a bit in this register will clear the event and the corresponding RIS bit also gets cleared. If the corresponding IMASK bit is set, then the corresponding MIS register bit also gets cleared.

Table 5-14 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hClears PWRDWNIFG interrupt
0h = Writing a 0 has no effect
1h = Clear interrupt
2PWRUPIFGR/W0hClears PWRUPIFG interrupt
0h = Writing a 0 has no effect
1h = Clear interrupt
1RXIFGR/W0hClears RXIFG interrupt
0h = Writing a 0 has no effect
1h = Clear interrupt
0TXIFGR/W0hClears TXIFG interrupt
0h = Writing a 0 has no effect
1h = Clear interrupt

5.10.7 IMSET Register (Offset = 6Ch) [Reset = 00000000h]

IMSET is shown in Table 5-15.

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Interrupt mask set register. Writing a 1 to a bit in this register will set the corresponding IMASK bit.

Table 5-15 IMSET Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hSet PWRDWNIFG interrupt mask
0h = Writing a 0 has no effect
1h = Set interrupt mask
2PWRUPIFGR/W0hSet PWRUPIFG interrupt mask
0h = Writing a 0 has no effect
1h = Set interrupt mask
1RXIFGR/W0hSet RXIFG interrupt mask
0h = Writing a 0 has no effect
1h = Set interrupt mask
0TXIFGR/W0hSet TXIFG interrupt mask
0h = Writing a 0 has no effect
1h = Set interrupt mask

5.10.8 IMCLR Register (Offset = 74h) [Reset = 00000000h]

IMCLR is shown in Table 5-16.

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Interrupt mask clear register. Writing a 1 to a bit in this register will clear the corresponding IMASK bit.

Table 5-16 IMCLR Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3PWRDWNIFGR/W0hClears PWRDWNIFG interrupt mask
0h = Writing a 0 has no effect
1h = IMASK bit corresponding to PWRDWNIFG is cleared
2PWRUPIFGR/W0hClears PWRUPIFG interrupt mask
0h = Writing a 0 has no effect
1h = IMASK bit corresponding to PWRUPIFG is cleared
1RXIFGR/W0hClears RXIFG interrupt mask
0h = Writing a 0 has no effect
1h = IMASK bit corresponding to RXIFG is cleared
0TXIFGR/W0hClears TXIFG interrupt mask
0h = Writing a 0 has no effect
1h = IMASK bit corresponding to TXIFG is cleared

5.10.9 TXD Register (Offset = 100h) [Reset = 00000000h]

TXD is shown in Table 5-17.

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Transmit data register. This register is used for sending SACI (SECAP command interface) data from the host to the device.
The host (SWD interface) can write this register. This updates the value of TXD, and sets TXCTL.TXDSTA = FULL
The host should only write TXD while TXCTL.TXDSTA = EMPTY.
If the host incorrectly writes TXD while TXCTL.TXDSTA = FULL, this will just update the value of TXD.
The host (SWD interface) can read the TXD register. This does not affect TXCTL.TXDSTA.
The device (boot code) can only read the TXD register. This sets TXCTL.TXDSTA = EMPTY.
The device should only read TXD while TXCTL.TXDSTA = FULL.
If the device incorrectly reads TXD while TXCTL.TXDSTA = EMPTY, this will just return the value of TXD.
If the host writes TXD on the same clock cycle as the device reads TXD:
The device reads the old TXD value.
TXD is updated with the new value, and TXCTL.TXDSTA is set to FULL.

Table 5-17 TXD Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hSACI command/parameter word. Valid value when TXCTL.TXDSTA=1. TXCTL.TXDSTA gets automatically cleared upon read.

5.10.10 TXCTL Register (Offset = 104h) [Reset = 00000000h]

TXCTL is shown in Table 5-18.

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Transmit control register. This register contains status of the TXD register (full/empty), and also software defined flags that are used by the SACI protocol.
The host (SWD interface) can write the FLAGS field of the TXCTL register.
The host (SWD interface) can read the TXCTL register.
The device (boot code) can only read the TXCTL register.

Table 5-18 TXCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-1FLAGSR0hSoftware defined flags that are used by the SACI protocol (host to device).
0TXDSTAR0hIndicates whether the host has written a word to the TXD register, which can be read by the device:
TXDSTA is automatically set upon write to TXD register in SECAP and automatically gets cleared upon read from TXD
0h = The TXD register does not contain a new SACI parameter word from the host, and should not be read by the device.
1h = The TXD register contains a new SACI parameter word from the host, which can be read by the device.

5.10.11 RXD Register (Offset = 108h) [Reset = 00000000h]

RXD is shown in Table 5-19.

Return to the Summary Table.

Receive data register. This register is used to send SACI command response data from the device to the host.
The device (boot code) can write the RXD register. This updates the value of RXD, and sets RXCTL.RXDSTA = FULL.
The device should only write RXD while RXCTL.RXDSTA = EMPTY.
If the device incorrectly writes RXD while RXCTL.RXDSTA = FULL, this will just update the value of RXD.
The device (boot code) can read the RXD register in order to flush it. This sets RXCTL.RXDSTA = EMPTY.
The host (SWD interface) can only read the RXD register. This sets RXCTL.RXDSTA = EMPTY.
The host should only read RXD while RXCTL.RXDSTA = FULL.
If the host incorrectly reads RXD while RXCTL.RXDSTA = EMPTY, this will just return the value of RXD.
If the device writes RXD on the same clock cycle as the host reads RXD:
The host reads the old RXD value.
RXD is updated with the new value, and RXCTL.RXDSTA is set to FULL.

Table 5-19 RXD Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hSACI command response word. RXCTL.RXDSTA automatically set upon write. RXCTL.RXDSTA automatically cleared upon read (flush operation).

5.10.12 RXCTL Register (Offset = 10Ch) [Reset = 00000000h]

RXCTL is shown in Table 5-20.

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Receive control register. This register contains status of the RXD register (full/empty), and also software defined flags that are used by the SACI protocol.
The device (boot code) can write the FLAGS field of the RXCTL register.
The device (boot code) can read the RXCTL register.
The host (SWD interface) can only read the RXCTL register

Table 5-20 RXCTL Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-1FLAGSR/W0hSoftware defined flags that are used by the SACI protocol (device to host).
0RXDSTAR0hIndicates whether the device has written a word to the RXD register, which can be read by the host:
RXDSTA is automatically set upon write to RXD and automatically cleared upon read from RXD register of SECAP or RXD.
0h = The RXD register does not contain a new SACI response word from the device, and should not be read by the host.
1h = The RXD register contains a new SACI response word from the device, which can be read by the host.

5.10.13 TXDPEEK Register (Offset = 110h) [Reset = 00000000h]

TXDPEEK is shown in Table 5-21.

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Transmit data peek register . This register is a read-only version of the TXD register that can be read by host and device without any side-effects.
This register is used to peek at the values in TXD without affecting the FULL/EMPTY flag.

Table 5-21 TXDPEEK Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hTransmit Data Peek Register. SACI command parameter word. TXCTL.TXDSTA not affected by read of TXDPEEK

5.10.14 RXDPEEK Register (Offset = 114h) [Reset = 00000000h]

RXDPEEK is shown in Table 5-22.

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Receive data peek register. The RXDPEEK register is a read-only version of the RXD register that can be read by host and device without any side-effects
This register is used to peek at the values in Receive Data Register without affecting the FULL/EMPTY flag.

Table 5-22 RXDPEEK Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR0hReceive Data Peek Register. SACI command response word. RXCTL.RXDSTA not affected by read of RXDPEEK

5.10.15 SPECIAL_AUTH Register (Offset = 200h) [Reset = 00000013h]

SPECIAL_AUTH is shown in Table 5-23.

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This register indicates the status of different AP firewalls.

Table 5-23 SPECIAL_AUTH Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6DBGDISR0hIndicates status of DBGDIS.
0h = Enables debugging capability.
1h = Disables debugging capability
5AHBAPENR0hIndicates status of AHBAPEN
0h = Disable AHB-AP
1h = Enable AHB-AP
4CFGAPENR1hIndicates status of CFGAPEN
0h = Disable CFG-AP
1h = Enable CFG-AP
3RESERVEDR0hReserved
2DFTAPENR0hIndicates status of DFTAPEN
0h = Disable DFT-TAP
1h = Enable DFT-TAP
1RESERVEDR1hReserved
0SECAPENR1hIndicates status of SECAP
0h = Disable SEC-AP
1h = Enable SEC-AP

5.10.16 SPECIAL_AUTH_SET Register (Offset = 204h) [Reset = 00000013h]

SPECIAL_AUTH_SET is shown in Table 5-24.

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This register is used for setting bits in SPECIAL_AUTH register.
This register is configured and locked during device boot.

Table 5-24 SPECIAL_AUTH_SET Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThis field must be configured with 0xA5 in order to access this register.
A5h = This field must be written with 0xA5 to be able to set any of the enable bits
23-7RESERVEDR0hReserved
6DBGDISW0hThis bit sets DBGDIS in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = SET DBGDIS
5AHBAPENW0hThis bit sets AHBAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = SET AHB-AP
4CFGAPENW1hThis bit sets CFGAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Set CFGAPEN
3RESERVEDW0hReserved
2DFTAPENW0hThis bit sets DFTAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Set DFTAPEN
1RESERVEDW1hReserved
0SECAPENW1hThis bit sets SECAPEN bit in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Set SECAPEN

5.10.17 SPECIAL_AUTH_CLR Register (Offset = 208h) [Reset = 00000000h]

SPECIAL_AUTH_CLR is shown in Table 5-25.

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This register is used for clearing bits in SPECIAL_AUTH register.
This register is configured and locked during device boot.

Table 5-25 SPECIAL_AUTH_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThis field must be configured with 0x22 in order to access this register.
22h = This field must be written with 0x22 to be able to clear any of the enable bits
23-7RESERVEDR0hReserved
6DBGDISW0hThis bit clears DBGDIS in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Clear DBGDIS
5AHBAPENW0hThis bit clears AHBAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Clear AHBAPEN
4CFGAPENW0hThis bit clears CFGAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Clear CFGAPEN
3RESERVEDW0hReserved
2DFTAPENW0hThis bit clears DFTAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Clear DFTAPEN
1RESERVEDW0hReserved
0SECAPENW0hThis bit clears SECAPEN in SPECIAL_AUTH register.
0h = Writing 0 has no effect
1h = Clear SECAPEN

5.10.18 APP_AUTH Register (Offset = 210h) [Reset = 00000000h]

APP_AUTH is shown in Table 5-26.

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This register indicates the debug privileges of ARM Cortex CPU.

Table 5-26 APP_AUTH Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1NIDENR0hControls non-invasive debug enable.
0h = Non-invasive debug disabled
1h = Non-invasive debug enabled
0DBGENR0hControls invasive debug enable.
0h = Invasive debug disabled
1h = Invasive debug enabled

5.10.19 APP_AUTH_SET Register (Offset = 214h) [Reset = 00000000h]

APP_AUTH_SET is shown in Table 5-27.

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This register is used for setting bits in APP_AUTH register.
This register is configured and locked during device boot.

Table 5-27 APP_AUTH_SET Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThis field must be configured with 0x39 in order to access this register.
39h = Write this value 0x39 to unlock writing to the APP_AUTH_SET register
23-2RESERVEDR/W0hReserved
1NIDENW0hSets NIDEN bit in [APP_AUTH ]register.
0h = Writing 0 has no effect
1h = Sets NIDEN
0DBGENW0hSets DBGEN bit in APP_AUTH register.
0h = Writing 0 has no effect
1h = Sets DBGEN

5.10.20 APP_AUTH_CLR Register (Offset = 218h) [Reset = 00000000h]

APP_AUTH_CLR is shown in Table 5-28.

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This register is used for clearing bits in APP_AUTH register.
This register is configured and locked during device boot.

Table 5-28 APP_AUTH_CLR Register Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hThis field must be configured with 0x7D in order to access this register.
7Dh = Write this value 0x7D to unlock writing to the APP_AUTH_CLR register
23-2RESERVEDR/W0hReserved
1NIDENW0hClears NIDEN bit in APP_AUTH register.
0h = Writing 0 has no effect
1h = Clears NIDEN
0DBGENW0hClears DBGEN bit in APP_AUTH register.
0h = Writing 0 has no effect
1h = Clears DBGEN

5.10.21 DBGCTL Register (Offset = 21Ch) [Reset = 00000020h]

DBGCTL is shown in Table 5-29.

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Debug control register. This register is used for controlling debug connection and read out debug status.

Table 5-29 DBGCTL Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0hReserved
5SWDCENR/W1hThis bit is used to enable connection between SWD pads and IceMelter (wakeup circuit used for detecting debug probe)
0h = Connection disabled
1h = Connection enabled
4DBGPWRUPACKR0hThis bit field specifies the status of dbgpwrupack from pmctl.
0h = dbgpwrupreq is not acknowledged
1h = dbgpwrupreq is acknowledged.
3SYSPWRUPACKR0hThis bit field specify the status of syspwrupack from pmctl.
0h = syspwrupreq is not acknowledged
1h = syspwrupreq is acknowledged
2JTAGSELR0hThis bit field specifies the status of JTAG MODE for TEST TAP.
0h = TEST TAP disabled
1h = TEST TAP enabled
1SWDSELR0hThis bit field specifies the status of SWD MODE for connection.
0h = debug connection disabled.
1h = debug connection enabled.
0SWDOVRR/W0hThis bit is used for connecting to IO pads to SWCLK/IO on SW-DP through a software request and establish SWD connection without IceMelter trigger for debug purpose.
0h = Transparent mode in which SWD connection is established via IceMelter Sequence.
1h = Force 1 or debug enable mode in which SWD connection is established bypassing IceMelter sequence