SWCU193A April 2023 – August 2024 CC2340R2 , CC2340R5 , CC2340R5-Q1
Table 6-71 lists the memory-mapped registers for the PMCTL registers. All register offset addresses not listed in Table 6-71 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | DESC | Description Register. | Go |
4h | DESCEX | Extended Description Register. | Go |
8h | SHTDWN | Shutdown Register. | Go |
Ch | SLPCTL | Sleep Control Register. | Go |
10h | WUSTA | Wakeup Status Register | Go |
14h | VDDRCTL | VDDR Control Register. | Go |
20h | SYSFSET | Internal. Only to be used through TI provided API. | Go |
24h | SYSFCLR | Internal. Only to be used through TI provided API. | Go |
28h | SYSFSTA | Internal. Only to be used through TI provided API. | Go |
2Ch | RSTCTL | Reset Control Register. | Go |
30h | RSTSTA | Reset Status. | Go |
34h | BOOTSTA | Internal. Only to be used through TI provided API. | Go |
3Ch | AONRSTA1 | AON Register Status 1. | Go |
40h | AONRSET1 | AON Register Set 1. | Go |
44h | AONRCLR1 | AON Register Clear 1. | Go |
64h | ETPP | Internal. Only to be used through TI provided API. | Go |
7Ch | RETCFG0 | Internal. Only to be used through TI provided API. | Go |
80h | RETCFG1 | Internal. Only to be used through TI provided API. | Go |
84h | RETCFG2 | Internal. Only to be used through TI provided API. | Go |
88h | RETCFG3 | Internal. Only to be used through TI provided API. | Go |
8Ch | RETCFG4 | Internal. Only to be used through TI provided API. | Go |
90h | RETCFG5 | Internal. Only to be used through TI provided API. | Go |
94h | RETCFG6 | Internal. Only to be used through TI provided API. | Go |
98h | RETCFG7 | Internal. Only to be used through TI provided API. | Go |
Complex bit access types are encoded to fit into small table cells. Table 6-72 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
DESC is shown in Table 6-73.
Return to the Summary Table.
Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | D741h | Module identifier used to uniquely identify this IP. |
15-12 | STDIPOFF | R | 0h | Standard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB. 0: Standard IP MMRs do not exist 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address) |
11-8 | INSTIDX | R | 0h | IP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15). |
7-4 | MAJREV | R | 1h | Major revision of IP (0-15). |
3-0 | MINREV | R | 0h | Minor revision of IP (0-15). |
DESCEX is shown in Table 6-74.
Return to the Summary Table.
Extended Description Register.
This register shows ULL IP availability and memory size configuration.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | FLASHSZ | R | 3h | System flash availability
0h = Flash size set to level 0 (Min size) 1h = Flash size set to level 1 2h = Flash size set to level 2 3h = Flash size set to level 3 (Max size) |
29-28 | SRAMSZ | R | 3h | System SRAM availability
0h = SRAM size set to level 0 (Min size) 1h = SRAM size set to level 1 2h = SRAM size set to level 2 3h = SRAM size set to level 3 (Max size) |
27 | TSD | R | 1h | TSD (thermal shutdown) IP status on device
0h = IP is unavailable 1h = IP is available |
26 | LPCMP | R | 1h | LPCMP (low power comparator) IP status on device
0h = IP is unavailable 1h = IP is available |
25-0 | RESERVED | R | 0h | Reserved |
SHTDWN is shown in Table 6-75.
Return to the Summary Table.
Shutdown Register.
This register controls SHUTDOWN mode entry.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | KEY | W | 0h | Setting a valid key will trigger the device to enter SHUTDOWN mode.
A5A5h = This is the only valid key value that will trigger SHUTDOWN mode. All other values are invalid and will have no effect. |
SLPCTL is shown in Table 6-76.
Return to the Summary Table.
Sleep Control Register.
This register controls I/O pad sleep mode. When I/O pad sleep mode is enabled all I/O pad outputs and I/O pad configurations are latched. Inputs are transparent if I/O pad is configured as input.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | SLPN | R/W | 0h | The boot code will set this bit field and disable sleep mode, automatically unless waking up from a SHUTDOWN RSTSTA.SDDET is set. Application software must reconfigure the state for all IO's before setting this bit field upon waking up from a SHUTDOWN to avoid glitches on pins. 0h = I/O pad sleep mode is enabled 1h = I/O pad sleep mode is disabled |
WUSTA is shown in Table 6-77.
Return to the Summary Table.
Wakeup Status Register
This register shows the device wakeup source. Used to distinguish between wakeup from STANDBY, SHUTDOWN and reset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | SRC | R | 1h | This field shows the device wakeup source.
1h = Wakeup from system reset / SHUTDOWN mode. See RSTSTA for more status information. 2h = Wakeup from STANDBY mode. |
VDDRCTL is shown in Table 6-78.
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VDDR Control Register.
This register contains VDDR regulator settings for the device.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | STBY | R/W | 0h | Select between continuous or duty-cycled VDDR regulation in STANDBY mode.
0h = Duty-cycled VDDR regulation in STANDBY mode. 1h = Continuous VDDR regulation in STANDBY mode. |
0 | SELECT | R/W | 0h | Select between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY mode).
0h = GLDO enabled for regulation of VDDR voltage 1h = DCDC enabled for regulation of VDDR voltage |
SYSFSET is shown in Table 6-79.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | FLAG2 | W | 0h | Internal. Only to be used through TI provided API. |
1 | FLAG1 | W | 0h | Internal. Only to be used through TI provided API. |
0 | FLAG0 | W | 0h | Internal. Only to be used through TI provided API. |
SYSFCLR is shown in Table 6-80.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | FLAG2 | W | 0h | Internal. Only to be used through TI provided API. |
1 | FLAG1 | W | 0h | Internal. Only to be used through TI provided API. |
0 | FLAG0 | W | 0h | Internal. Only to be used through TI provided API. |
SYSFSTA is shown in Table 6-81.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | FLAG2 | R | 0h | Internal. Only to be used through TI provided API. |
1 | FLAG1 | R | 0h | Internal. Only to be used through TI provided API. |
0 | FLAG0 | R | 0h | Internal. Only to be used through TI provided API. |
RSTCTL is shown in Table 6-82.
Return to the Summary Table.
Reset Control Register.
This register configures and controls system reset.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | LFLOSS | R/W | 0h | LF clock loss reset enable. Trigger system reset when LF clock loss is detected, which reset the entire device and causes a reboot of the system. The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to LFLOSSEV. 0h = LF clock loss detection will not trigger a system reset. 1h = LF clock loss detection will trigger a system reset. |
1 | TSDEN | R/W | 0h | TSD (Thermal Shutdown) enable. TSD will trigger an immediate system reset, which reset the entire device and causes a reboot of the system. The device will be in reset until released by the TSD IP. The system reset event is captured as RSTSTA.TSDEV flag set. 0h = No effect 1h = Temperature shutdown comparator enable. Note: If TSD IP not present, see DESCEX.TSD, enable will have no effect. |
0 | SYSRST | R/W | 0h | Trigger system reset, which will reset the entire device and causes a reboot of the system. The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to SYSRSTEV. 0h = No effect 1h = Trigger a system reset. |
RSTSTA is shown in Table 6-83.
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Reset Status.
This register contains the reset source and SHUTDOWN wakeup source for the system.
Check WUSTA.SRC first to ensure that wakeup from STANDBY is not set.
The capture feature is not rearmed until all of the possible reset sources have been released and the result has been copied to this register.
During the copy and rearm process it is one 24MHz period in which an eventual new system reset will be reported as Power on reset regardless of the root cause.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17 | SDDET | R | 0h | Wakeup from SHUTDOWN flag. Note: This flag will be cleared when SLPCTL.SLPN is asserted. 0h = Wakeup from SHUTDOWN mode not triggered 1h = Wakeup from SHUTDOWN mode |
16 | IOWUSD | R | 0h | Wakeup from SHUTDOWN on an I/O event flag. Note: This flag will be cleared when SLPCTL.SLPN is asserted. 0h = Wakeup from SHUTDOWN not triggered by an I/O event. 1h = Wakeup from SHUTDOWN triggered by an I/O event. |
15-8 | RESERVED | R | 0h | Reserved |
7-4 | SYSSRC | R | 0h | Shows which reset event that triggered SYSRESET in RESETSRC
0h = LF clock loss event 1h = CPU reset event 2h = CPU LOCKUP event 3h = Watchdog timeout event 4h = System reset event 5h = Serial Wire Debug reset event 6h = Analog FSM timeout event Eh = Analog Error reset event Fh = Digital Error reset event |
3 | TSDEV | R | 0h | System reset triggered by TSD event
0h = TSD event not triggered 1h = System reset triggered by TSD event |
2-0 | RESETSRC | R | 0h | Shows the root cause of the last system reset. More than one reported reset source can have been active during the last system reset, but only the root cause is reported. If reset cause is SYSRESET or PINRESET, the other reset flags must be read to determine actual root cause. 0h = Power on reset 1h = Reset pin. TSD will also trigger a pin reset, so actual root cause is given by TSDEV reset flag status. 2h = Brown out detect on VDDS 4h = Brown out detect on VDDR 6h = Digital system reset. Actual root cause is given by SYSSRC. |
BOOTSTA is shown in Table 6-84.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | FLAG | R/W | 0h | Internal. Only to be used through TI provided API. |
AONRSTA1 is shown in Table 6-85.
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AON Register Status 1.
This register contains the general purpose AON flags for SW, and is updated through AONRSET1.FLAG and AONRCLR1.FLAG.
The register is only reset on a POR event.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | 0h | Reserved |
17-0 | FLAG | R | 0h | State of the AON register flags |
AONRSET1 is shown in Table 6-86.
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AON Register Set 1.
This register sets the AON flags that can be read through AONRSTA1.FLAG.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | Reserved |
17-0 | FLAG | W | 0h | Write 1 to set AONRSTA1.FLAG
0h = No flags changed status 0003FFFFh = Set all flags |
AONRCLR1 is shown in Table 6-87.
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AON Register Clear 1.
This register clears the AON flags that can be read through AONRSTA1.FLAG.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | 0h | Reserved |
17-0 | FLAG | W | 0h | Write 1 to clear AONRSTA1.FLAG
0h = No flags changed status 0003FFFFh = Clear all flags |
ETPP is shown in Table 6-88.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RETCFG0 is shown in Table 6-89.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 1h | Internal. Only to be used through TI provided API. |
RETCFG1 is shown in Table 6-90.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VAL | R/W | 0h | Internal. Only to be used through TI provided API. |
RETCFG2 is shown in Table 6-91.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | VAL | R/W | 2h | Internal. Only to be used through TI provided API. |
RETCFG3 is shown in Table 6-92.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RETCFG4 is shown in Table 6-93.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RETCFG5 is shown in Table 6-94.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RETCFG6 is shown in Table 6-95.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |
RETCFG7 is shown in Table 6-96.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved |