SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 20-217 lists the memory-mapped registers for the AUX_SPIM registers. All register offset addresses not listed in Table 20-217 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | SPIMCFG | SPI Master Configuration | Section 20.8.10.1 |
4h | MISOCFG | MISO Configuration | Section 20.8.10.2 |
8h | MOSICTL | MOSI Control | Section 20.8.10.3 |
Ch | TX8 | Transmit 8 Bit | Section 20.8.10.4 |
10h | TX16 | Transmit 16 Bit | Section 20.8.10.5 |
14h | RX8 | Receive 8 Bit | Section 20.8.10.6 |
18h | RX16 | Receive 16 Bit | Section 20.8.10.7 |
1Ch | SCLKIDLE | SCLK Idle | Section 20.8.10.8 |
20h | DATAIDLE | Data Idle | Section 20.8.10.9 |
Complex bit access types are encoded to fit into small table cells. Table 20-218 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
SPIMCFG is shown in Table 20-219.
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SPI Master Configuration
Write operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-2 | DIV | R/W | 0h | SCLK divider. Peripheral clock frequency division gives the SCLK clock frequency. The division factor equals (2 * (DIV+1)): 0x00: Divide by 2. 0x01: Divide by 4. 0x02: Divide by 6. ... 0x3F: Divide by 128. |
1 | PHA | R/W | 0h | Phase of the MOSI and MISO data signals. 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) edges of SCLK. 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) edges of SCLK. |
0 | POL | R/W | 0h | Polarity of the SCLK signal. 0: SCLK is low when idle, first clock edge rises. 1: SCLK is high when idle, first clock edge falls. |
MISOCFG is shown in Table 20-220.
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MISO Configuration
Write operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4-0 | AUXIO | R/W | 0h | AUXIO to MISO mux. Select the AUXIO pin that connects to MISO. |
MOSICTL is shown in Table 20-221.
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MOSI Control
Write operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | VALUE | W | 0h | MOSI level control. 0: Set MOSI low. 1: Set MOSI high. |
TX8 is shown in Table 20-222.
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Transmit 8 Bit
Write operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | W | 0h | 8 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
TX16 is shown in Table 20-223.
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Transmit 16 Bit
Write operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | DATA | W | 0h | 16 bit data transfer. Write DATA to start transfer, MSB first. When transfer completes, MOSI stays at the value of LSB. |
RX8 is shown in Table 20-224.
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Receive 8 Bit
Read operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | DATA | R | 0h | Latest 8 bits received on MISO. |
RX16 is shown in Table 20-225.
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Receive 16 Bit
Read operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | DATA | R | 0h | Latest 16 bits received on MISO. |
SCLKIDLE is shown in Table 20-226.
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SCLK Idle
Read operation stalls until SCLK is idle with no remaining clock edges.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 1h | Wait for SCLK idle. Read operation stalls until SCLK is idle with no remaining clock edges. Read then returns 1. AUX_SCE can use this to control CS deassertion. |
DATAIDLE is shown in Table 20-227.
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Data Idle
Read operation stalls until current transfer completes.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | STAT | R | 1h | Wait for data idle. Read operation stalls until the SCLK period associated with LSB transmission completes. Read then returns 1. AUX_SCE can use this to control CS deassertion. |