SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-56 lists the memory-mapped registers for the CPU_DWT registers. All register offset addresses not listed in Table 2-56 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CTRL | Provides configuration and status information for the DWT unit, and used to control features of the unit | Section 2.5.2.1 |
4h | CYCCNT | Shows or sets the value of the processor cycle counter, CYCCNT | Section 2.5.2.2 |
8h | CPICNT | CPI Count Register | Section 2.5.2.3 |
Ch | EXCCNT | Counts the total cycles spent in exception processing | Section 2.5.2.4 |
10h | SLEEPCNT | Sleep Count Register | Section 2.5.2.5 |
14h | LSUCNT | Increments on the additional cycles required to execute all load or store instructions | Section 2.5.2.6 |
18h | FOLDCNT | Increments on the additional cycles required to execute all load or store instructions | Section 2.5.2.7 |
1Ch | PCSR | Program Counter Sample Register | Section 2.5.2.8 |
28h | FUNCTION0 | Controls the operation of watchpoint comparator 0 | Section 2.5.2.9 |
38h | FUNCTION1 | Controls the operation of watchpoint comparator 1 | Section 2.5.2.10 |
48h | FUNCTION2 | Controls the operation of watchpoint comparator 2 | Section 2.5.2.11 |
58h | FUNCTION3 | Controls the operation of watchpoint comparator 3 | Section 2.5.2.12 |
FBCh | DEVARCH | Provides CoreSight discovery information for the DWT | Section 2.5.2.13 |
FCCh | DEVTYPE | Provides CoreSight discovery information for the DWT | Section 2.5.2.14 |
FD0h | PIDR4 | Provides CoreSight discovery information for the DWT | Section 2.5.2.15 |
FD4h | PIDR5 | Provides CoreSight discovery information for the DWT | Section 2.5.2.16 |
FD8h | PIDR6 | Provides CoreSight discovery information for the DWT | Section 2.5.2.17 |
FDCh | PIDR7 | Provides CoreSight discovery information for the DWT | Section 2.5.2.18 |
FE0h | PIDR0 | Provides CoreSight discovery information for the DWT | Section 2.5.2.19 |
FE4h | PIDR1 | Provides CoreSight discovery information for the DWT | Section 2.5.2.20 |
FE8h | PIDR2 | Provides CoreSight discovery information for the DWT | Section 2.5.2.21 |
FECh | PIDR3 | Provides CoreSight discovery information for the DWT | Section 2.5.2.22 |
FF0h | CIDR0 | Provides CoreSight discovery information for the DWT | Section 2.5.2.23 |
FF4h | CIDR1 | Provides CoreSight discovery information for the DWT | Section 2.5.2.24 |
FF8h | CIDR2 | Provides CoreSight discovery information for the DWT | Section 2.5.2.25 |
FFCh | CIDR3 | Provides CoreSight discovery information for the DWT | Section 2.5.2.26 |
Complex bit access types are encoded to fit into small table cells. Table 2-57 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTRL is shown in Table 2-58.
Return to the Summary Table.
Provides configuration and status information for the DWT unit, and used to control features of the unit
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | NUMCOMP | R | 0h | Number of DWT comparators implemented |
27 | NOTRCPKT | R | 0h | Indicates whether the implementation does not support trace |
26 | NOEXTTRIG | R | 0h | Reserved, RAZ |
25 | NOCYCCNT | R | 0h | Indicates whether the implementation does not include a cycle counter |
24 | NOPRFCNT | R | 0h | Indicates whether the implementation does not include the profiling counters |
23 | CYCDISS | R | 0h | Controls whether the cycle counter is disabled in Secure state |
22 | CYCEVTENA | R | 0h | Enables Event Counter packet generation on POSTCNT underflow |
21 | FOLDEVTENA | R | 0h | Enables DWT_FOLDCNT counter |
20 | LSUEVTENA | R | 0h | Enables DWT_LSUCNT counter |
19 | SLEEPEVTENA | R | 0h | Enable DWT_SLEEPCNT counter |
18 | EXCEVTENA | R | 0h | Enables DWT_EXCCNT counter |
17 | CPIEVTENA | R | 0h | Enables DWT_CPICNT counter |
16 | EXTTRCENA | R | 0h | Enables generation of Exception Trace packets |
15-13 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
12 | PCSAMPLENA | R | 0h | Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation |
11-10 | SYNCTAP | R | 0h | Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate |
9 | CYCTAP | R | 0h | Selects the position of the POSTCNT tap on the CYCCNT counter |
8-5 | POSTINIT | R | 0h | Initial value for the POSTCNT counter |
4-1 | POSTPRESET | R | 0h | Reload value for the POSTCNT counter |
0 | CYCCNTENA | R | 0h | Enables CYCCNT |
CYCCNT is shown in Table 2-59.
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Shows or sets the value of the processor cycle counter, CYCCNT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CYCCNT | R/W | 0h | Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero |
CPICNT is shown in Table 2-60.
Return to the Summary Table.
CPI Count Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | CPICNT | R/W | 0h | Counts one on each cycle when all of the following are true: - DWT_CTRL.CPIEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed. - No load-store operation is in progress, see DWT_LSUCNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - The PE is not in a power saving mode, see DWT_SLEEPCNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. |
EXCCNT is shown in Table 2-61.
Return to the Summary Table.
Counts the total cycles spent in exception processing
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | EXCCNT | R/W | 0h | Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. |
SLEEPCNT is shown in Table 2-62.
Return to the Summary Table.
Sleep Count Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | SLEEPCNT | R/W | 0h | Counts one on each cycle when all of the following are true: - DWT_CTRL.SLEEPEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No load-store operation is in progress, see DWT_LSUCNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - The PE is in a power saving mode. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. |
LSUCNT is shown in Table 2-63.
Return to the Summary Table.
Increments on the additional cycles required to execute all load or store instructions
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | LSUCNT | R/W | 0h | Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE. |
FOLDCNT is shown in Table 2-64.
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Increments on the additional cycles required to execute all load or store instructions
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | FOLDCNT | R/W | 0h | Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one |
PCSR is shown in Table 2-65.
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Program Counter Sample Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | EIASAMPLE | R | 0h | The possible values of this field are: 0xFFFFFFFF One of the following is true: - The PE is halted in Debug state. - The Security Extension is implemented, the sampled instruction was executed in Secure state, and SecureNoninvasiveDebugAllowed() == FALSE. - NoninvasiveDebugAllowed() == FALSE. - DEMCR.TRCENA == 0. - The address of a recently-executed instruction is not available. Not 0xFFFFFFFF Instruction address of a recently executed instruction. Bit [0] of the sample instruction address is 0. |
FUNCTION0 is shown in Table 2-66.
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Controls the operation of watchpoint comparator 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | ID | R | 0h | Identifies the capabilities for MATCH for comparator *n |
26-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
24 | MATCHED | R | 0h | Set to 1 when the comparator matches |
23-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11-10 | DATAVSIZE | R/W | 0h | Defines the size of the object being watched for by Data Value and Data Address comparators |
9-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5-4 | ACTION | R/W | 0h | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH |
3-0 | MATCH | R/W | 0h | Controls the type of match generated by this comparator |
FUNCTION1 is shown in Table 2-67.
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Controls the operation of watchpoint comparator 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | ID | R | 0h | Identifies the capabilities for MATCH for comparator *n |
26-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
24 | MATCHED | R | 0h | Set to 1 when the comparator matches |
23-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11-10 | DATAVSIZE | R/W | 0h | Defines the size of the object being watched for by Data Value and Data Address comparators |
9-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5-4 | ACTION | R/W | 0h | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH |
3-0 | MATCH | R/W | 0h | Controls the type of match generated by this comparator |
FUNCTION2 is shown in Table 2-68.
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Controls the operation of watchpoint comparator 2
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | ID | R | 0h | Identifies the capabilities for MATCH for comparator *n |
26-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
24 | MATCHED | R | 0h | Set to 1 when the comparator matches |
23-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11-10 | DATAVSIZE | R/W | 0h | Defines the size of the object being watched for by Data Value and Data Address comparators |
9-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5-4 | ACTION | R/W | 0h | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH |
3-0 | MATCH | R/W | 0h | Controls the type of match generated by this comparator |
FUNCTION3 is shown in Table 2-69.
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Controls the operation of watchpoint comparator 3
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | ID | R | 0h | Identifies the capabilities for MATCH for comparator *n |
26-25 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
24 | MATCHED | R | 0h | Set to 1 when the comparator matches |
23-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11-10 | DATAVSIZE | R/W | 0h | Defines the size of the object being watched for by Data Value and Data Address comparators |
9-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5-4 | ACTION | R/W | 0h | Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH |
3-0 | MATCH | R/W | 0h | Controls the type of match generated by this comparator |
DEVARCH is shown in Table 2-70.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | ARCHITECT | R | 0h | Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. |
20 | PRESENT | R | 0h | Defines that the DEVARCH register is present |
19-16 | REVISION | R | 0h | Defines the architecture revision of the component |
15-12 | ARCHVER | R | 0h | Defines the architecture version of the component |
11-0 | ARCHPART | R | 0h | Defines the architecture of the component |
DEVTYPE is shown in Table 2-71.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | SUB | R | 0h | Component sub-type |
3-0 | MAJOR | R | 0h | Component major type |
PIDR4 is shown in Table 2-72.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | SIZE | R | 0h | See CoreSight Architecture Specification |
3-0 | DES_2 | R | 0h | See CoreSight Architecture Specification |
PIDR5 is shown in Table 2-73.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
PIDR6 is shown in Table 2-74.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
PIDR7 is shown in Table 2-75.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
PIDR0 is shown in Table 2-76.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | PART_0 | R | 0h | See CoreSight Architecture Specification |
PIDR1 is shown in Table 2-77.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | DES_0 | R | 0h | See CoreSight Architecture Specification |
3-0 | PART_1 | R | 0h | See CoreSight Architecture Specification |
PIDR2 is shown in Table 2-78.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | REVISION | R | 0h | See CoreSight Architecture Specification |
3 | JEDEC | R | 0h | See CoreSight Architecture Specification |
2-0 | DES_1 | R | 0h | See CoreSight Architecture Specification |
PIDR3 is shown in Table 2-79.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | REVAND | R | 0h | See CoreSight Architecture Specification |
3-0 | CMOD | R | 0h | See CoreSight Architecture Specification |
CIDR0 is shown in Table 2-80.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | PRMBL_0 | R | 0h | See CoreSight Architecture Specification |
CIDR1 is shown in Table 2-81.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | CLASS | R | 0h | See CoreSight Architecture Specification |
3-0 | PRMBL_1 | R | 0h | See CoreSight Architecture Specification |
CIDR2 is shown in Table 2-82.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | PRMBL_2 | R | 0h | See CoreSight Architecture Specification |
CIDR3 is shown in Table 2-83.
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Provides CoreSight discovery information for the DWT
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | PRMBL_3 | R | 0h | See CoreSight Architecture Specification |