SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 5-16 lists the memory-mapped registers for the EVENT registers. All register offset addresses not listed in Table 5-16 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CPUIRQSEL0 | Output Selection for CPU Interrupt 0 | Section 5.8.2.1 |
4h | CPUIRQSEL1 | Output Selection for CPU Interrupt 1 | Section 5.8.2.2 |
8h | CPUIRQSEL2 | Output Selection for CPU Interrupt 2 | Section 5.8.2.3 |
Ch | CPUIRQSEL3 | Output Selection for CPU Interrupt 3 | Section 5.8.2.4 |
10h | CPUIRQSEL4 | Output Selection for CPU Interrupt 4 | Section 5.8.2.5 |
14h | CPUIRQSEL5 | Output Selection for CPU Interrupt 5 | Section 5.8.2.6 |
18h | CPUIRQSEL6 | Output Selection for CPU Interrupt 6 | Section 5.8.2.7 |
1Ch | CPUIRQSEL7 | Output Selection for CPU Interrupt 7 | Section 5.8.2.8 |
20h | CPUIRQSEL8 | Output Selection for CPU Interrupt 8 | Section 5.8.2.9 |
24h | CPUIRQSEL9 | Output Selection for CPU Interrupt 9 | Section 5.8.2.10 |
28h | CPUIRQSEL10 | Output Selection for CPU Interrupt 10 | Section 5.8.2.11 |
2Ch | CPUIRQSEL11 | Output Selection for CPU Interrupt 11 | Section 5.8.2.12 |
30h | CPUIRQSEL12 | Output Selection for CPU Interrupt 12 | Section 5.8.2.13 |
34h | CPUIRQSEL13 | Output Selection for CPU Interrupt 13 | Section 5.8.2.14 |
38h | CPUIRQSEL14 | Output Selection for CPU Interrupt 14 | Section 5.8.2.15 |
3Ch | CPUIRQSEL15 | Output Selection for CPU Interrupt 15 | Section 5.8.2.16 |
40h | CPUIRQSEL16 | Output Selection for CPU Interrupt 16 | Section 5.8.2.17 |
44h | CPUIRQSEL17 | Output Selection for CPU Interrupt 17 | Section 5.8.2.18 |
48h | CPUIRQSEL18 | Output Selection for CPU Interrupt 18 | Section 5.8.2.19 |
4Ch | CPUIRQSEL19 | Output Selection for CPU Interrupt 19 | Section 5.8.2.20 |
50h | CPUIRQSEL20 | Output Selection for CPU Interrupt 20 | Section 5.8.2.21 |
54h | CPUIRQSEL21 | Output Selection for CPU Interrupt 21 | Section 5.8.2.22 |
58h | CPUIRQSEL22 | Output Selection for CPU Interrupt 22 | Section 5.8.2.23 |
5Ch | CPUIRQSEL23 | Output Selection for CPU Interrupt 23 | Section 5.8.2.24 |
60h | CPUIRQSEL24 | Output Selection for CPU Interrupt 24 | Section 5.8.2.25 |
64h | CPUIRQSEL25 | Output Selection for CPU Interrupt 25 | Section 5.8.2.26 |
68h | CPUIRQSEL26 | Output Selection for CPU Interrupt 26 | Section 5.8.2.27 |
6Ch | CPUIRQSEL27 | Output Selection for CPU Interrupt 27 | Section 5.8.2.28 |
70h | CPUIRQSEL28 | Output Selection for CPU Interrupt 28 | Section 5.8.2.29 |
74h | CPUIRQSEL29 | Output Selection for CPU Interrupt 29 | Section 5.8.2.30 |
78h | CPUIRQSEL30 | Output Selection for CPU Interrupt 30 | Section 5.8.2.31 |
7Ch | CPUIRQSEL31 | Output Selection for CPU Interrupt 31 | Section 5.8.2.32 |
80h | CPUIRQSEL32 | Output Selection for CPU Interrupt 32 | Section 5.8.2.33 |
84h | CPUIRQSEL33 | Output Selection for CPU Interrupt 33 | Section 5.8.2.34 |
88h | CPUIRQSEL34 | Output Selection for CPU Interrupt 34 | Section 5.8.2.35 |
8Ch | CPUIRQSEL35 | Output Selection for CPU Interrupt 35 | Section 5.8.2.36 |
90h | CPUIRQSEL36 | Output Selection for CPU Interrupt 36 | Section 5.8.2.37 |
94h | CPUIRQSEL37 | Output Selection for CPU Interrupt 37 | Section 5.8.2.38 |
98h | CPUIRQSEL38 | Output Selection for CPU Interrupt 38 | Section 5.8.2.39 |
9Ch | CPUIRQSEL39 | Output Selection for CPU Interrupt 39 | Section 5.8.2.40 |
A0h | CPUIRQSEL40 | Output Selection for CPU Interrupt 40 | Section 5.8.2.41 |
A4h | CPUIRQSEL41 | Output Selection for CPU Interrupt 41 | Section 5.8.2.42 |
A8h | CPUIRQSEL42 | Output Selection for CPU Interrupt 42 | Section 5.8.2.43 |
100h | RFCSEL0 | Output Selection for RFC Event 0 | Section 5.8.2.44 |
104h | RFCSEL1 | Output Selection for RFC Event 1 | Section 5.8.2.45 |
108h | RFCSEL2 | Output Selection for RFC Event 2 | Section 5.8.2.46 |
10Ch | RFCSEL3 | Output Selection for RFC Event 3 | Section 5.8.2.47 |
110h | RFCSEL4 | Output Selection for RFC Event 4 | Section 5.8.2.48 |
114h | RFCSEL5 | Output Selection for RFC Event 5 | Section 5.8.2.49 |
118h | RFCSEL6 | Output Selection for RFC Event 6 | Section 5.8.2.50 |
11Ch | RFCSEL7 | Output Selection for RFC Event 7 | Section 5.8.2.51 |
120h | RFCSEL8 | Output Selection for RFC Event 8 | Section 5.8.2.52 |
124h | RFCSEL9 | Output Selection for RFC Event 9 | Section 5.8.2.53 |
200h | GPT0ACAPTSEL | Output Selection for GPT0 0 | Section 5.8.2.54 |
204h | GPT0BCAPTSEL | Output Selection for GPT0 1 | Section 5.8.2.55 |
300h | GPT1ACAPTSEL | Output Selection for GPT1 0 | Section 5.8.2.56 |
304h | GPT1BCAPTSEL | Output Selection for GPT1 1 | Section 5.8.2.57 |
400h | GPT2ACAPTSEL | Output Selection for GPT2 0 | Section 5.8.2.58 |
404h | GPT2BCAPTSEL | Output Selection for GPT2 1 | Section 5.8.2.59 |
508h | UDMACH1SSEL | Output Selection for DMA Channel 1 SREQ | Section 5.8.2.60 |
50Ch | UDMACH1BSEL | Output Selection for DMA Channel 1 REQ | Section 5.8.2.61 |
510h | UDMACH2SSEL | Output Selection for DMA Channel 2 SREQ | Section 5.8.2.62 |
514h | UDMACH2BSEL | Output Selection for DMA Channel 2 REQ | Section 5.8.2.63 |
518h | UDMACH3SSEL | Output Selection for DMA Channel 3 SREQ | Section 5.8.2.64 |
51Ch | UDMACH3BSEL | Output Selection for DMA Channel 3 REQ | Section 5.8.2.65 |
520h | UDMACH4SSEL | Output Selection for DMA Channel 4 SREQ | Section 5.8.2.66 |
524h | UDMACH4BSEL | Output Selection for DMA Channel 4 REQ | Section 5.8.2.67 |
528h | UDMACH5SSEL | Output Selection for DMA Channel 5 SREQ | Section 5.8.2.68 |
52Ch | UDMACH5BSEL | Output Selection for DMA Channel 5 REQ | Section 5.8.2.69 |
530h | UDMACH6SSEL | Output Selection for DMA Channel 6 SREQ | Section 5.8.2.70 |
534h | UDMACH6BSEL | Output Selection for DMA Channel 6 REQ | Section 5.8.2.71 |
538h | UDMACH7SSEL | Output Selection for DMA Channel 7 SREQ | Section 5.8.2.72 |
53Ch | UDMACH7BSEL | Output Selection for DMA Channel 7 REQ | Section 5.8.2.73 |
540h | UDMACH8SSEL | Output Selection for DMA Channel 8 SREQ | Section 5.8.2.74 |
544h | UDMACH8BSEL | Output Selection for DMA Channel 8 REQ | Section 5.8.2.75 |
548h | UDMACH9SSEL | Output Selection for DMA Channel 9 SREQ | Section 5.8.2.76 |
54Ch | UDMACH9BSEL | Output Selection for DMA Channel 9 REQ | Section 5.8.2.77 |
550h | UDMACH10SSEL | Output Selection for DMA Channel 10 SREQ | Section 5.8.2.78 |
554h | UDMACH10BSEL | Output Selection for DMA Channel 10 REQ | Section 5.8.2.79 |
558h | UDMACH11SSEL | Output Selection for DMA Channel 11 SREQ | Section 5.8.2.80 |
55Ch | UDMACH11BSEL | Output Selection for DMA Channel 11 REQ | Section 5.8.2.81 |
560h | UDMACH12SSEL | Output Selection for DMA Channel 12 SREQ | Section 5.8.2.82 |
564h | UDMACH12BSEL | Output Selection for DMA Channel 12 REQ | Section 5.8.2.83 |
56Ch | UDMACH13BSEL | Output Selection for DMA Channel 13 REQ | Section 5.8.2.84 |
574h | UDMACH14BSEL | Output Selection for DMA Channel 14 REQ | Section 5.8.2.85 |
57Ch | UDMACH15BSEL | Output Selection for DMA Channel 15 REQ | Section 5.8.2.86 |
580h | UDMACH16SSEL | Output Selection for DMA Channel 16 SREQ | Section 5.8.2.87 |
584h | UDMACH16BSEL | Output Selection for DMA Channel 16 REQ | Section 5.8.2.88 |
588h | UDMACH17SSEL | Output Selection for DMA Channel 17 SREQ | Section 5.8.2.89 |
58Ch | UDMACH17BSEL | Output Selection for DMA Channel 17 REQ | Section 5.8.2.90 |
598h | UDMACH19SSEL | Output Selection for DMA Channel 19 SREQ | Section 5.8.2.91 |
59Ch | UDMACH19BSEL | Output Selection for DMA Channel 19 REQ | Section 5.8.2.92 |
5A0h | UDMACH20SSEL | Output Selection for DMA Channel 20 SREQ | Section 5.8.2.93 |
5A4h | UDMACH20BSEL | Output Selection for DMA Channel 20 REQ | Section 5.8.2.94 |
5A8h | UDMACH21SSEL | Output Selection for DMA Channel 21 SREQ | Section 5.8.2.95 |
5ACh | UDMACH21BSEL | Output Selection for DMA Channel 21 REQ | Section 5.8.2.96 |
5B0h | UDMACH22SSEL | Output Selection for DMA Channel 22 SREQ | Section 5.8.2.97 |
5B4h | UDMACH22BSEL | Output Selection for DMA Channel 22 REQ | Section 5.8.2.98 |
5B8h | UDMACH23SSEL | Output Selection for DMA Channel 23 SREQ | Section 5.8.2.99 |
5BCh | UDMACH23BSEL | Output Selection for DMA Channel 23 REQ | Section 5.8.2.100 |
5C0h | UDMACH24SSEL | Output Selection for DMA Channel 24 SREQ | Section 5.8.2.101 |
5C4h | UDMACH24BSEL | Output Selection for DMA Channel 24 REQ | Section 5.8.2.102 |
5C8h | UDMACH25SSEL | Output Selection for DMA Channel 25 SREQ | Section 5.8.2.103 |
5CCh | UDMACH25BSEL | Output Selection for DMA Channel 25 REQ | Section 5.8.2.104 |
5D0h | UDMACH26SSEL | Output Selection for DMA Channel 26 SREQ | Section 5.8.2.105 |
5D4h | UDMACH26BSEL | Output Selection for DMA Channel 26 REQ | Section 5.8.2.106 |
5E0h | UDMACH28SSEL | Output Selection for DMA Channel 28 SREQ | Section 5.8.2.107 |
5E4h | UDMACH28BSEL | Output Selection for DMA Channel 28 REQ | Section 5.8.2.108 |
5E8h | UDMACH29SSEL | Output Selection for DMA Channel 29 SREQ | Section 5.8.2.109 |
5ECh | UDMACH29BSEL | Output Selection for DMA Channel 29 REQ | Section 5.8.2.110 |
5F0h | UDMACH30SSEL | Output Selection for DMA Channel 30 SREQ | Section 5.8.2.111 |
5F4h | UDMACH30BSEL | Output Selection for DMA Channel 30 REQ | Section 5.8.2.112 |
5F8h | UDMACH31SSEL | Output Selection for DMA Channel 31 SREQ | Section 5.8.2.113 |
5FCh | UDMACH31BSEL | Output Selection for DMA Channel 31 REQ | Section 5.8.2.114 |
600h | GPT3ACAPTSEL | Output Selection for GPT3 0 | Section 5.8.2.115 |
604h | GPT3BCAPTSEL | Output Selection for GPT3 1 | Section 5.8.2.116 |
700h | AUXSEL0 | Output Selection for AUX Subscriber 0 | Section 5.8.2.117 |
800h | CM3NMISEL0 | Output Selection for NMI Subscriber 0 | Section 5.8.2.118 |
900h | I2SSTMPSEL0 | Output Selection for I2S Subscriber 0 | Section 5.8.2.119 |
A00h | FRZSEL0 | Output Selection for FRZ Subscriber | Section 5.8.2.120 |
F00h | SWEV | Set or Clear Software Events | Section 5.8.2.121 |
Complex bit access types are encoded to fit into small table cells. Table 5-17 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CPUIRQSEL0 is shown in Table 5-18.
Return to the Summary Table.
Output Selection for CPU Interrupt 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 4h | Read only selection value
4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings |
CPUIRQSEL1 is shown in Table 5-19.
Return to the Summary Table.
Output Selection for CPU Interrupt 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 9h | Read only selection value
9h = Interrupt event from I2C |
CPUIRQSEL2 is shown in Table 5-20.
Return to the Summary Table.
Output Selection for CPU Interrupt 2
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Eh | Read only selection value
1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event |
CPUIRQSEL3 is shown in Table 5-21.
Return to the Summary Table.
Output Selection for CPU Interrupt 3
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Fh | Read only selection value
1Fh = PKA Interrupt event |
CPUIRQSEL4 is shown in Table 5-22.
Return to the Summary Table.
Output Selection for CPU Interrupt 4
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7h | Read only selection value
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting |
CPUIRQSEL5 is shown in Table 5-23.
Return to the Summary Table.
Output Selection for CPU Interrupt 5
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 24h | Read only selection value
24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS |
CPUIRQSEL6 is shown in Table 5-24.
Return to the Summary Table.
Output Selection for CPU Interrupt 6
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Ch | Read only selection value
1Ch = AUX software event 0, triggered by AUX_EVCTL:SWEVSET.SWEV0, also available as AUX_EVENT0 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL |
CPUIRQSEL7 is shown in Table 5-25.
Return to the Summary Table.
Output Selection for CPU Interrupt 7
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 22h | Read only selection value
22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS |
CPUIRQSEL8 is shown in Table 5-26.
Return to the Summary Table.
Output Selection for CPU Interrupt 8
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 23h | Read only selection value
23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS |
CPUIRQSEL9 is shown in Table 5-27.
Return to the Summary Table.
Output Selection for CPU Interrupt 9
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Bh | Read only selection value
1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event |
CPUIRQSEL10 is shown in Table 5-28.
Return to the Summary Table.
Output Selection for CPU Interrupt 10
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Ah | Read only selection value
1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG |
CPUIRQSEL11 is shown in Table 5-29.
Return to the Summary Table.
Output Selection for CPU Interrupt 11
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 19h | Read only selection value
19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG |
CPUIRQSEL12 is shown in Table 5-30.
Return to the Summary Table.
Output Selection for CPU Interrupt 12
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8h | Read only selection value
8h = Interrupt event from I2S |
CPUIRQSEL13 is shown in Table 5-31.
Return to the Summary Table.
Output Selection for CPU Interrupt 13
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1Dh | Read only selection value
1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL |
CPUIRQSEL14 is shown in Table 5-32.
Return to the Summary Table.
Output Selection for CPU Interrupt 14
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 18h | Read only selection value
18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN |
CPUIRQSEL15 is shown in Table 5-33.
Return to the Summary Table.
Output Selection for CPU Interrupt 15
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 10h | Read only selection value
10h = GPT0A interrupt event, controlled by GPT0:TAMR |
CPUIRQSEL16 is shown in Table 5-34.
Return to the Summary Table.
Output Selection for CPU Interrupt 16
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 11h | Read only selection value
11h = GPT0B interrupt event, controlled by GPT0:TBMR |
CPUIRQSEL17 is shown in Table 5-35.
Return to the Summary Table.
Output Selection for CPU Interrupt 17
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 12h | Read only selection value
12h = GPT1A interrupt event, controlled by GPT1:TAMR |
CPUIRQSEL18 is shown in Table 5-36.
Return to the Summary Table.
Output Selection for CPU Interrupt 18
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 13h | Read only selection value
13h = GPT1B interrupt event, controlled by GPT1:TBMR |
CPUIRQSEL19 is shown in Table 5-37.
Return to the Summary Table.
Output Selection for CPU Interrupt 19
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | Ch | Read only selection value
Ch = GPT2A interrupt event, controlled by GPT2:TAMR |
CPUIRQSEL20 is shown in Table 5-38.
Return to the Summary Table.
Output Selection for CPU Interrupt 20
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | Dh | Read only selection value
Dh = GPT2B interrupt event, controlled by GPT2:TBMR |
CPUIRQSEL21 is shown in Table 5-39.
Return to the Summary Table.
Output Selection for CPU Interrupt 21
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | Eh | Read only selection value
Eh = GPT3A interrupt event, controlled by GPT3:TAMR |
CPUIRQSEL22 is shown in Table 5-40.
Return to the Summary Table.
Output Selection for CPU Interrupt 22
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | Fh | Read only selection value
Fh = GPT3B interrupt event, controlled by GPT3:TBMR |
CPUIRQSEL23 is shown in Table 5-41.
Return to the Summary Table.
Output Selection for CPU Interrupt 23
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 5Dh | Read only selection value
5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL |
CPUIRQSEL24 is shown in Table 5-42.
Return to the Summary Table.
Output Selection for CPU Interrupt 24
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 27h | Read only selection value
27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE |
CPUIRQSEL25 is shown in Table 5-43.
Return to the Summary Table.
Output Selection for CPU Interrupt 25
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 26h | Read only selection value
26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS |
CPUIRQSEL26 is shown in Table 5-44.
Return to the Summary Table.
Output Selection for CPU Interrupt 26
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 15h | Read only selection value
15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT |
CPUIRQSEL27 is shown in Table 5-45.
Return to the Summary Table.
Output Selection for CPU Interrupt 27
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 64h | Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0 |
CPUIRQSEL28 is shown in Table 5-46.
Return to the Summary Table.
Output Selection for CPU Interrupt 28
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | Bh | Read only selection value
Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS |
CPUIRQSEL29 is shown in Table 5-47.
Return to the Summary Table.
Output Selection for CPU Interrupt 29
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 1h | Read only selection value
1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV |
CPUIRQSEL30 is shown in Table 5-48.
Return to the Summary Table.
Output Selection for CPU Interrupt 30
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 0h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 8h = Interrupt event from I2S Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 14h = DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ 16h = DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 5Eh = CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted |
CPUIRQSEL31 is shown in Table 5-49.
Return to the Summary Table.
Output Selection for CPU Interrupt 31
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 6Ah | Read only selection value
6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA |
CPUIRQSEL32 is shown in Table 5-50.
Return to the Summary Table.
Output Selection for CPU Interrupt 32
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 73h | Read only selection value
73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS |
CPUIRQSEL33 is shown in Table 5-51.
Return to the Summary Table.
Output Selection for CPU Interrupt 33
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 68h | Read only selection value
68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN |
CPUIRQSEL34 is shown in Table 5-52.
Return to the Summary Table.
Output Selection for CPU Interrupt 34
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 6h | Read only selection value
6h = Combined event from Oscillator control |
CPUIRQSEL35 is shown in Table 5-53.
Return to the Summary Table.
Output Selection for CPU Interrupt 35
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 38h | Read only selection value
38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 |
CPUIRQSEL36 is shown in Table 5-54.
Return to the Summary Table.
Output Selection for CPU Interrupt 36
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 25h | Read only selection value
25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS |
CPUIRQSEL37 is shown in Table 5-55.
Return to the Summary Table.
Output Selection for CPU Interrupt 37
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 5h | Read only selection value
5h = Combined event from battery monitor |
CPUIRQSEL38 is shown in Table 5-56.
Return to the Summary Table.
Output Selection for CPU Interrupt 38
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Ah | Read only selection value
7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS |
CPUIRQSEL39 is shown in Table 5-57.
Return to the Summary Table.
Output Selection for CPU Interrupt 39
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Bh | Read only selection value
7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS |
CPUIRQSEL40 is shown in Table 5-58.
Return to the Summary Table.
Output Selection for CPU Interrupt 40
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Ch | Read only selection value
7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS |
CPUIRQSEL41 is shown in Table 5-59.
Return to the Summary Table.
Output Selection for CPU Interrupt 41
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Dh | Read only selection value
7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS |
CPUIRQSEL42 is shown in Table 5-60.
Return to the Summary Table.
Output Selection for CPU Interrupt 42
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Eh | Read only selection value
7Eh = Interrupt event from I2C1 |
RFCSEL0 is shown in Table 5-61.
Return to the Summary Table.
Output Selection for RFC Event 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 3Dh | Read only selection value
3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT |
RFCSEL1 is shown in Table 5-62.
Return to the Summary Table.
Output Selection for RFC Event 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 3Eh | Read only selection value
3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT |
RFCSEL2 is shown in Table 5-63.
Return to the Summary Table.
Output Selection for RFC Event 2
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 3Fh | Read only selection value
3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT |
RFCSEL3 is shown in Table 5-64.
Return to the Summary Table.
Output Selection for RFC Event 3
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 40h | Read only selection value
40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT |
RFCSEL4 is shown in Table 5-65.
Return to the Summary Table.
Output Selection for RFC Event 4
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 41h | Read only selection value
41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT |
RFCSEL5 is shown in Table 5-66.
Return to the Summary Table.
Output Selection for RFC Event 5
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 42h | Read only selection value
42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT |
RFCSEL6 is shown in Table 5-67.
Return to the Summary Table.
Output Selection for RFC Event 6
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 43h | Read only selection value
43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT |
RFCSEL7 is shown in Table 5-68.
Return to the Summary Table.
Output Selection for RFC Event 7
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 44h | Read only selection value
44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT |
RFCSEL8 is shown in Table 5-69.
Return to the Summary Table.
Output Selection for RFC Event 8
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 77h | Read only selection value
77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN |
RFCSEL9 is shown in Table 5-70.
Return to the Summary Table.
Output Selection for RFC Event 9
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 2h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 8h = Interrupt event from I2S Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL 64h = Software event 0, triggered by SWEV.SWEV0 65h = Software event 1, triggered by SWEV.SWEV1 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS |
GPT0ACAPTSEL is shown in Table 5-71.
Return to the Summary Table.
Output Selection for GPT0 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 55h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. 56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT0BCAPTSEL is shown in Table 5-72.
Return to the Summary Table.
Output Selection for GPT0 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 56h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. 56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT1ACAPTSEL is shown in Table 5-73.
Return to the Summary Table.
Output Selection for GPT1 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 57h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. 58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT1BCAPTSEL is shown in Table 5-74.
Return to the Summary Table.
Output Selection for GPT1 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 58h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. 58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT2ACAPTSEL is shown in Table 5-75.
Return to the Summary Table.
Output Selection for GPT2 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 59h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT2BCAPTSEL is shown in Table 5-76.
Return to the Summary Table.
Output Selection for GPT2 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 5Ah | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
UDMACH1SSEL is shown in Table 5-77.
Return to the Summary Table.
Output Selection for DMA Channel 1 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 31h | Read only selection value
31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE |
UDMACH1BSEL is shown in Table 5-78.
Return to the Summary Table.
Output Selection for DMA Channel 1 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 30h | Read only selection value
30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE |
UDMACH2SSEL is shown in Table 5-79.
Return to the Summary Table.
Output Selection for DMA Channel 2 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 33h | Read only selection value
33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE |
UDMACH2BSEL is shown in Table 5-80.
Return to the Summary Table.
Output Selection for DMA Channel 2 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 32h | Read only selection value
32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE |
UDMACH3SSEL is shown in Table 5-81.
Return to the Summary Table.
Output Selection for DMA Channel 3 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 29h | Read only selection value
29h = SPI0 RX DMA single request, controlled by SPI0:DMACR.RXDMAE |
UDMACH3BSEL is shown in Table 5-82.
Return to the Summary Table.
Output Selection for DMA Channel 3 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 28h | Read only selection value
28h = SPI0 RX DMA burst request , controlled by SPI0:DMACR.RXDMAE |
UDMACH4SSEL is shown in Table 5-83.
Return to the Summary Table.
Output Selection for DMA Channel 4 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Bh | Read only selection value
2Bh = SPI0 TX DMA single request, controlled by SPI0:DMACR.TXDMAE |
UDMACH4BSEL is shown in Table 5-84.
Return to the Summary Table.
Output Selection for DMA Channel 4 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Ah | Read only selection value
2Ah = SPI0 TX DMA burst request , controlled by SPI0:DMACR.TXDMAE |
UDMACH5SSEL is shown in Table 5-85.
Return to the Summary Table.
Output Selection for DMA Channel 5 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 35h | Read only selection value
35h = UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE |
UDMACH5BSEL is shown in Table 5-86.
Return to the Summary Table.
Output Selection for DMA Channel 5 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 34h | Read only selection value
34h = UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE |
UDMACH6SSEL is shown in Table 5-87.
Return to the Summary Table.
Output Selection for DMA Channel 6 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 37h | Read only selection value
37h = UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE |
UDMACH6BSEL is shown in Table 5-88.
Return to the Summary Table.
Output Selection for DMA Channel 6 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 36h | Read only selection value
36h = UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE |
UDMACH7SSEL is shown in Table 5-89.
Return to the Summary Table.
Output Selection for DMA Channel 7 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 75h | Read only selection value
75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL |
UDMACH7BSEL is shown in Table 5-90.
Return to the Summary Table.
Output Selection for DMA Channel 7 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 76h | Read only selection value
76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL |
UDMACH8SSEL is shown in Table 5-91.
Return to the Summary Table.
Output Selection for DMA Channel 8 SREQ
Single request is ignored for this channel
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 74h | Read only selection value
74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START |
UDMACH8BSEL is shown in Table 5-92.
Return to the Summary Table.
Output Selection for DMA Channel 8 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 74h | Read only selection value
74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START |
UDMACH9SSEL is shown in Table 5-93.
Return to the Summary Table.
Output Selection for DMA Channel 9 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 45h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 45h = Not used tied to 0 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH9BSEL is shown in Table 5-94.
Return to the Summary Table.
Output Selection for DMA Channel 9 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMAARIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 4Dh | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH10SSEL is shown in Table 5-95.
Return to the Summary Table.
Output Selection for DMA Channel 10 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 46h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 46h = Not used tied to 0 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH10BSEL is shown in Table 5-96.
Return to the Summary Table.
Output Selection for DMA Channel 10 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT0 as GPT0:RIS.DMABRIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 4Eh | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH11SSEL is shown in Table 5-97.
Return to the Summary Table.
Output Selection for DMA Channel 11 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 47h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 47h = Not used tied to 0 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH11BSEL is shown in Table 5-98.
Return to the Summary Table.
Output Selection for DMA Channel 11 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMAARIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 4Fh | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH12SSEL is shown in Table 5-99.
Return to the Summary Table.
Output Selection for DMA Channel 12 SREQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 48h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 48h = Not used tied to 0 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH12BSEL is shown in Table 5-100.
Return to the Summary Table.
Output Selection for DMA Channel 12 REQ
DMA_DONE for the corresponding DMA channel is available as interrupt on GPT1 as GPT1:RIS.DMABRIS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 50h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 79h = Always asserted |
UDMACH13BSEL is shown in Table 5-101.
Return to the Summary Table.
Output Selection for DMA Channel 13 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 3h | Read only selection value
3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV |
UDMACH14BSEL is shown in Table 5-102.
Return to the Summary Table.
Output Selection for DMA Channel 14 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 1h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 1h = AON programmable event 0. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG0_EV 2h = AON programmable event 1. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG1_EV 3h = AON programmable event 2. Event selected by AON_EVENT MCU event selector, AON_EVENT:EVTOMCUSEL.AON_PROG2_EV 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 8h = Interrupt event from I2S 9h = Interrupt event from I2C Ah = AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS Ch = GPT2A interrupt event, controlled by GPT2:TAMR Dh = GPT2B interrupt event, controlled by GPT2:TBMR Eh = GPT3A interrupt event, controlled by GPT3:TAMR Fh = GPT3B interrupt event, controlled by GPT3:TBMR 10h = GPT0A interrupt event, controlled by GPT0:TAMR 11h = GPT0B interrupt event, controlled by GPT0:TBMR 12h = GPT1A interrupt event, controlled by GPT1:TAMR 13h = GPT1B interrupt event, controlled by GPT1:TBMR 14h = DMA done for software tiggered UDMA channel 0, see UDMA0:SOFTREQ 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 16h = DMA done for software tiggered UDMA channel 18, see UDMA0:SOFTREQ 18h = Watchdog interrupt event, controlled by WDT:CTL.INTEN 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Dh = AUX software event 1, triggered by AUX_EVCTL:SWEVSET.SWEV1, also available as AUX_EVENT2 AON wake up event. MCU domain wakeup control AON_EVENT:MCUWUSEL 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 1Fh = PKA Interrupt event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 26h = DMA bus error, corresponds to UDMA0:ERROR.STATUS 27h = Combined DMA done, corresponding flags are here UDMA0:REQDONE 28h = SPI0 RX DMA burst request , controlled by SPI0:DMACR.RXDMAE 29h = SPI0 RX DMA single request, controlled by SPI0:DMACR.RXDMAE 2Ah = SPI0 TX DMA burst request , controlled by SPI0:DMACR.TXDMAE 2Bh = SPI0 TX DMA single request, controlled by SPI0:DMACR.TXDMAE 2Ch = SPI1 RX DMA burst request , controlled by SPI0:DMACR.RXDMAE 2Dh = SPI1 RX DMA single request, controlled by SPI0:DMACR.RXDMAE 2Eh = SPI1 TX DMA burst request , controlled by SPI0:DMACR.TXDMAE 2Fh = SPI1 TX DMA single request, controlled by SPI0:DMACR.TXDMAE 30h = UART0 RX DMA burst request, controlled by UART0:DMACTL.RXDMAE 31h = UART0 RX DMA single request, controlled by UART0:DMACTL.RXDMAE 32h = UART0 TX DMA burst request, controlled by UART0:DMACTL.TXDMAE 33h = UART0 TX DMA single request, controlled by UART0:DMACTL.TXDMAE 34h = UART1 RX DMA burst request, controlled by UART1:DMACTL.RXDMAE 35h = UART1 RX DMA single request, controlled by UART1:DMACTL.RXDMAE 36h = UART1 TX DMA burst request, controlled by UART1:DMACTL.TXDMAE 37h = UART1 TX DMA single request, controlled by UART1:DMACTL.TXDMAE 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 4Dh = GPT0A DMA trigger event. Configured by GPT0:DMAEV 4Eh = GPT0B DMA trigger event. Configured by GPT0:DMAEV 4Fh = GPT1A DMA trigger event. Configured by GPT1:DMAEV 50h = GPT1B DMA trigger event. Configured by GPT1:DMAEV 51h = GPT2A DMA trigger event. Configured by GPT2:DMAEV 52h = GPT2B DMA trigger event. Configured by GPT2:DMAEV 53h = GPT3A DMA trigger event. Configured by GPT3:DMAEV 54h = GPT3B DMA trigger event. Configured by GPT3:DMAEV 55h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT0 wil be routed here. 56h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT1 wil be routed here. 57h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT2 wil be routed here. 58h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT3 wil be routed here. 59h = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 5Ah = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT4 wil be routed here. 5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. 5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. 5Dh = CRYPTO result available interupt event, the corresponding flag is found here CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by CRYPTO:IRQSTAT.RESULT_AVAIL 5Eh = CRYPTO DMA input done event, the correspondingg flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled by CRYPTO:IRQEN.DMA_IN_DONE 63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE 64h = Software event 0, triggered by SWEV.SWEV0 65h = Software event 1, triggered by SWEV.SWEV1 66h = Software event 2, triggered by SWEV.SWEV2 67h = Software event 3, triggered by SWEV.SWEV3 68h = TRNG Interrupt event, controlled by TRNG:IRQEN.EN 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 74h = DMA sofware trigger from AUX, triggered by AUX_EVCTL:DMASWREQ.START 75h = DMA single request event from AUX, configured by AUX_EVCTL:DMACTL 76h = DMA burst request event from AUX, configured by AUX_EVCTL:DMACTL 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 78h = CPU halted 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 7Fh = SPI2 RX DMA burst request , controlled by SPI2:DMACR.RXDMAE 80h = SPI2 RX DMA single request, controlled by SPI2:DMACR.RXDMAE 81h = SPI2 TX DMA burst request , controlled by SPI2:DMACR.TXDMAE 82h = SPI2 TX DMA single request, controlled by SPI2:DMACR.TXDMAE 83h = SPI3 RX DMA burst request , controlled by SPI2:DMACR.RXDMAE 84h = SPI3 RX DMA single request, controlled by SPI2:DMACR.RXDMAE 85h = SPI3 TX DMA burst request , controlled by SPI2:DMACR.TXDMAE 86h = SPI3 TX DMA single request, controlled by SPI2:DMACR.TXDMAE 87h = UART2 RX DMA burst request, controlled by UART2:DMACTL.RXDMAE 88h = UART2 RX DMA single request, controlled by UART2:DMACTL.RXDMAE 89h = UART2 TX DMA burst request, controlled by UART2:DMACTL.TXDMAE 8Ah = UART2 TX DMA single request, controlled by UART2:DMACTL.TXDMAE 8Bh = UART3 RX DMA burst request, controlled by UART3:DMACTL.RXDMAE 8Ch = UART3 RX DMA single request, controlled by UART3:DMACTL.RXDMAE 8Dh = UART3 TX DMA burst request, controlled by UART3:DMACTL.TXDMAE 8Eh = UART3 TX DMA single request, controlled by UART3:DMACTL.TXDMAE |
UDMACH15BSEL is shown in Table 5-103.
Return to the Summary Table.
Output Selection for DMA Channel 15 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7h | Read only selection value
7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting |
UDMACH16SSEL is shown in Table 5-104.
Return to the Summary Table.
Output Selection for DMA Channel 16 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Dh | Read only selection value
2Dh = SPI1 RX DMA single request, controlled by SPI0:DMACR.RXDMAE |
UDMACH16BSEL is shown in Table 5-105.
Return to the Summary Table.
Output Selection for DMA Channel 16 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Ch | Read only selection value
2Ch = SPI1 RX DMA burst request , controlled by SPI0:DMACR.RXDMAE |
UDMACH17SSEL is shown in Table 5-106.
Return to the Summary Table.
Output Selection for DMA Channel 17 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Fh | Read only selection value
2Fh = SPI1 TX DMA single request, controlled by SPI0:DMACR.TXDMAE |
UDMACH17BSEL is shown in Table 5-107.
Return to the Summary Table.
Output Selection for DMA Channel 17 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 2Eh | Read only selection value
2Eh = SPI1 TX DMA burst request , controlled by SPI0:DMACR.TXDMAE |
UDMACH19SSEL is shown in Table 5-108.
Return to the Summary Table.
Output Selection for DMA Channel 19 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 80h | Read only selection value
80h = SPI2 RX DMA single request, controlled by SPI2:DMACR.RXDMAE |
UDMACH19BSEL is shown in Table 5-109.
Return to the Summary Table.
Output Selection for DMA Channel 19 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 7Fh | Read only selection value
7Fh = SPI2 RX DMA burst request , controlled by SPI2:DMACR.RXDMAE |
UDMACH20SSEL is shown in Table 5-110.
Return to the Summary Table.
Output Selection for DMA Channel 20 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 82h | Read only selection value
82h = SPI2 TX DMA single request, controlled by SPI2:DMACR.TXDMAE |
UDMACH20BSEL is shown in Table 5-111.
Return to the Summary Table.
Output Selection for DMA Channel 20 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 81h | Read only selection value
81h = SPI2 TX DMA burst request , controlled by SPI2:DMACR.TXDMAE |
UDMACH21SSEL is shown in Table 5-112.
Return to the Summary Table.
Output Selection for DMA Channel 21 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 64h | Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0 |
UDMACH21BSEL is shown in Table 5-113.
Return to the Summary Table.
Output Selection for DMA Channel 21 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 64h | Read only selection value
64h = Software event 0, triggered by SWEV.SWEV0 |
UDMACH22SSEL is shown in Table 5-114.
Return to the Summary Table.
Output Selection for DMA Channel 22 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 65h | Read only selection value
65h = Software event 1, triggered by SWEV.SWEV1 |
UDMACH22BSEL is shown in Table 5-115.
Return to the Summary Table.
Output Selection for DMA Channel 22 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 65h | Read only selection value
65h = Software event 1, triggered by SWEV.SWEV1 |
UDMACH23SSEL is shown in Table 5-116.
Return to the Summary Table.
Output Selection for DMA Channel 23 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 66h | Read only selection value
66h = Software event 2, triggered by SWEV.SWEV2 |
UDMACH23BSEL is shown in Table 5-117.
Return to the Summary Table.
Output Selection for DMA Channel 23 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 66h | Read only selection value
66h = Software event 2, triggered by SWEV.SWEV2 |
UDMACH24SSEL is shown in Table 5-118.
Return to the Summary Table.
Output Selection for DMA Channel 24 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 67h | Read only selection value
67h = Software event 3, triggered by SWEV.SWEV3 |
UDMACH24BSEL is shown in Table 5-119.
Return to the Summary Table.
Output Selection for DMA Channel 24 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 67h | Read only selection value
67h = Software event 3, triggered by SWEV.SWEV3 |
UDMACH25SSEL is shown in Table 5-120.
Return to the Summary Table.
Output Selection for DMA Channel 25 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 84h | Read only selection value
84h = SPI3 RX DMA single request, controlled by SPI2:DMACR.RXDMAE |
UDMACH25BSEL is shown in Table 5-121.
Return to the Summary Table.
Output Selection for DMA Channel 25 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 83h | Read only selection value
83h = SPI3 RX DMA burst request , controlled by SPI2:DMACR.RXDMAE |
UDMACH26SSEL is shown in Table 5-122.
Return to the Summary Table.
Output Selection for DMA Channel 26 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 86h | Read only selection value
86h = SPI3 TX DMA single request, controlled by SPI2:DMACR.TXDMAE |
UDMACH26BSEL is shown in Table 5-123.
Return to the Summary Table.
Output Selection for DMA Channel 26 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 85h | Read only selection value
85h = SPI3 TX DMA burst request , controlled by SPI2:DMACR.TXDMAE |
UDMACH28SSEL is shown in Table 5-124.
Return to the Summary Table.
Output Selection for DMA Channel 28 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 88h | Read only selection value
88h = UART2 RX DMA single request, controlled by UART2:DMACTL.RXDMAE |
UDMACH28BSEL is shown in Table 5-125.
Return to the Summary Table.
Output Selection for DMA Channel 28 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 87h | Read only selection value
87h = UART2 RX DMA burst request, controlled by UART2:DMACTL.RXDMAE |
UDMACH29SSEL is shown in Table 5-126.
Return to the Summary Table.
Output Selection for DMA Channel 29 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8Ah | Read only selection value
8Ah = UART2 TX DMA single request, controlled by UART2:DMACTL.TXDMAE |
UDMACH29BSEL is shown in Table 5-127.
Return to the Summary Table.
Output Selection for DMA Channel 29 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 89h | Read only selection value
89h = UART2 TX DMA burst request, controlled by UART2:DMACTL.TXDMAE |
UDMACH30SSEL is shown in Table 5-128.
Return to the Summary Table.
Output Selection for DMA Channel 30 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8Ch | Read only selection value
8Ch = UART3 RX DMA single request, controlled by UART3:DMACTL.RXDMAE |
UDMACH30BSEL is shown in Table 5-129.
Return to the Summary Table.
Output Selection for DMA Channel 30 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8Bh | Read only selection value
8Bh = UART3 RX DMA burst request, controlled by UART3:DMACTL.RXDMAE |
UDMACH31SSEL is shown in Table 5-130.
Return to the Summary Table.
Output Selection for DMA Channel 31 SREQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8Eh | Read only selection value
8Eh = UART3 TX DMA single request, controlled by UART3:DMACTL.TXDMAE |
UDMACH31BSEL is shown in Table 5-131.
Return to the Summary Table.
Output Selection for DMA Channel 31 REQ
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 8Dh | Read only selection value
8Dh = UART3 TX DMA burst request, controlled by UART3:DMACTL.TXDMAE |
GPT3ACAPTSEL is shown in Table 5-132.
Return to the Summary Table.
Output Selection for GPT3 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 5Bh | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. 5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
GPT3BCAPTSEL is shown in Table 5-133.
Return to the Summary Table.
Output Selection for GPT3 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 5Ch | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 4h = Edge detect event from IOC. Configureded by the IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET settings 5h = Combined event from battery monitor 6h = Combined event from Oscillator control 7h = Event from AON_RTC, controlled by the AON_RTC:CTL.COMB_EV_MASK setting 9h = Interrupt event from I2C Bh = AUX combined event, the corresponding flag register is here AUX_EVCTL:EVTOMCUFLAGS 15h = FLASH controller error event, the status flags are FLASH:FEDACSTAT.FSM_DONE and FLASH:FEDACSTAT.RVF_INT 19h = RFC Doorbell Command Acknowledgement Interrupt, equvialent to RFC_DBELL:RFACKIFG.ACKFLAG 1Ah = Combined RFC hardware interrupt, corresponding flag is here RFC_DBELL:RFHWIFG 1Bh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE0 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_0 event 1Eh = Combined Interrupt for CPE Generated events. Corresponding flags are here RFC_DBELL:RFCPEIFG. Only interrupts selected with CPE1 in RFC_DBELL:RFCPEIFG can trigger a RFC_CPE_1 event 22h = SPI0 combined interrupt, interrupt flags are found here SPI0:MIS 23h = SPI1 combined interrupt, interrupt flags are found here SPI1:MIS 24h = UART0 combined interrupt, interrupt flags are found here UART0:MIS 25h = UART1 combined interrupt, interrupt flags are found here UART1:MIS 38h = AUX Timer2 event 0, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 39h = AUX Timer2 event 1, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 3Ah = AUX Timer2 event 2, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 3Bh = AUX Timer2 event 3, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 3Ch = AUX Timer2 pulse, corresponding to flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 5Bh = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT6 wil be routed here. 5Ch = Port capture event from IOC, configured by IOC:IOCFGn.PORT_ID. Events on ports configured with ENUM PORT_EVENT7 wil be routed here. 69h = AON wakeup event, the corresponding flag is here AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV 6Ah = AUX Compare A event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA 6Bh = AUX Compare B event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB 6Ch = AUX TDC measurement done event, corresponds to the flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and the AUX_TDC status AUX_TDC:STAT.DONE 6Dh = AUX timer 0 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV 6Eh = AUX timer 1 event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV 6Fh = Autotake event from AUX semaphore, configured by AUX_SMPH:AUTOTAKE 70h = AUX ADC done, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE 71h = AUX ADC FIFO watermark event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL 72h = Loopback of OBSMUX0 through AUX, corresponds to AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 73h = AUX ADC interrupt event, corresponds to AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status flags are found here AUX_EVCTL:EVTOMCUFLAGS 77h = RTC periodic event controlled by AON_RTC:CTL.RTC_UPD_EN 79h = Always asserted 7Ah = SPI2 combined interrupt, interrupt flags are found here SPI2:MIS 7Bh = SPI3 combined interrupt, interrupt flags are found here SPI3:MIS 7Ch = UART2 combined interrupt, interrupt flags are found here UART2:MIS 7Dh = UART3 combined interrupt, interrupt flags are found here UART3:MIS 7Eh = Interrupt event from I2C1 |
AUXSEL0 is shown in Table 5-134.
Return to the Summary Table.
Output Selection for AUX Subscriber 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 10h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive Ch = GPT2A interrupt event, controlled by GPT2:TAMR Dh = GPT2B interrupt event, controlled by GPT2:TBMR Eh = GPT3A interrupt event, controlled by GPT3:TAMR Fh = GPT3B interrupt event, controlled by GPT3:TBMR 10h = GPT0A interrupt event, controlled by GPT0:TAMR 11h = GPT0B interrupt event, controlled by GPT0:TBMR 12h = GPT1A interrupt event, controlled by GPT1:TAMR 13h = GPT1B interrupt event, controlled by GPT1:TBMR 3Dh = GPT0A compare event. Configured by GPT0:TAMR.TCACT 3Eh = GPT0B compare event. Configured by GPT0:TBMR.TCACT 3Fh = GPT1A compare event. Configured by GPT1:TAMR.TCACT 40h = GPT1B compare event. Configured by GPT1:TBMR.TCACT 41h = GPT2A compare event. Configured by GPT2:TAMR.TCACT 42h = GPT2B compare event. Configured by GPT2:TBMR.TCACT 43h = GPT3A compare event. Configured by GPT3:TAMR.TCACT 44h = GPT3B compare event. Configured by GPT3:TBMR.TCACT 79h = Always asserted |
CM3NMISEL0 is shown in Table 5-135.
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Output Selection for NMI Subscriber 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R | 63h | Read only selection value
63h = Watchdog non maskable interrupt event, controlled by WDT:CTL.INTTYPE |
I2SSTMPSEL0 is shown in Table 5-136.
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Output Selection for I2S Subscriber 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 5Fh | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 79h = Always asserted |
FRZSEL0 is shown in Table 5-137.
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Output Selection for FRZ Subscriber
The halted debug signal is passed to peripherals such as the General Purpose Timer, Sensor Controller with Digital and Analog Peripherals (AUX), Radio, and RTC. When the system CPU halts, the connected peripherals that have freeze enabled also halt. The programmable output can be set to static values of 0 or 1, and can also be set to pass the halted signal.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | EV | R/W | 78h | Read/write selection value Writing any other value than values defined by a ENUM may result in undefined behavior. 0h = Always inactive 78h = CPU halted 79h = Always asserted |
SWEV is shown in Table 5-138.
Return to the Summary Table.
Set or Clear Software Events
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | SWEV3 | R/W | 0h | Writing "1" to this bit when the value is "0" triggers the Software 3 event. |
23-17 | RESERVED | R | 0h | Reserved |
16 | SWEV2 | R/W | 0h | Writing "1" to this bit when the value is "0" triggers the Software 2 event. |
15-9 | RESERVED | R | 0h | Reserved |
8 | SWEV1 | R/W | 0h | Writing "1" to this bit when the value is "0" triggers the Software 1 event. |
7-1 | RESERVED | R | 0h | Reserved |
0 | SWEV0 | R/W | 0h | Writing "1" to this bit when the value is "0" triggers the Software 0 event. |