SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 7-104 lists the memory-mapped registers for the DDI_0_OSC registers. All register offset addresses not listed in Table 7-104 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CTL0 | Control 0 | Section 7.8.3.1 |
4h | CTL1 | Control 1 | Section 7.8.3.2 |
8h | RADCEXTCFG | RADC External Configuration | Section 7.8.3.3 |
Ch | AMPCOMPCTL | Amplitude Compensation Control | Section 7.8.3.4 |
10h | AMPCOMPTH1 | Amplitude Compensation Threshold 1 | Section 7.8.3.5 |
14h | AMPCOMPTH2 | Amplitude Compensation Threshold 2 | Section 7.8.3.6 |
18h | ANABYPASSVAL1 | Analog Bypass Values 1 | Section 7.8.3.7 |
1Ch | ANABYPASSVAL2 | Internal | Section 7.8.3.8 |
20h | ATESTCTL | Analog Test Control | Section 7.8.3.9 |
24h | ADCDOUBLERNANOAMPCTL | ADC Doubler Nanoamp Control | Section 7.8.3.10 |
28h | XOSCHFCTL | XOSCHF Control | Section 7.8.3.11 |
2Ch | LFOSCCTL | Low Frequency Oscillator Control | Section 7.8.3.12 |
30h | RCOSCHFCTL | RCOSCHF Control | Section 7.8.3.13 |
34h | RCOSCMFCTL | RCOSC_MF Control | Section 7.8.3.14 |
3Ch | STAT0 | Status 0 | Section 7.8.3.15 |
40h | STAT1 | Status 1 | Section 7.8.3.16 |
44h | STAT2 | Status 2 | Section 7.8.3.17 |
Complex bit access types are encoded to fit into small table cells. Table 7-105 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTL0 is shown in Table 7-106.
Return to the Summary Table.
Control 0
Controls clock source selects
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | XTAL_IS_24M | R/W | 0h | Set based on the accurate high frequency XTAL. |
30 | RESERVED | R | 0h | Reserved |
29 | BYPASS_XOSC_LF_CLK_QUAL | R/W | 0h | Internal. Only to be used through TI provided API. |
28 | BYPASS_RCOSC_LF_CLK_QUAL | R/W | 0h | Internal. Only to be used through TI provided API. |
27-26 | DOUBLER_START_DURATION | R/W | 0h | Internal. Only to be used through TI provided API. |
25 | DOUBLER_RESET_DURATION | R/W | 0h | Internal. Only to be used through TI provided API. |
24 | CLK_DCDC_SRC_SEL | R/W | 0h | Select DCDC clock source. 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC 1: CLK_DCDC is always 48 MHz clock from RCOSC |
23-15 | RESERVED | R | 0h | Reserved |
14 | HPOSC_MODE_EN | R/W | 0h | 0: HPOSC mode is not enabled. The 48 MHz crystal is
required for radio operation. 1: Enables HPOSC mode. The internal HPOSC can be used as HF system clock and for radio operation. |
13 | RESERVED | R | 0h | Reserved |
12 | RCOSC_LF_TRIMMED | R/W | 0h | Internal. Only to be used through TI provided API. |
11 | XOSC_HF_POWER_MODE | R/W | 0h | Internal. Only to be used through TI provided API. |
10 | XOSC_LF_DIG_BYPASS | R/W | 0h | Bypass XOSC_LF and use the digital input clock from
AON for the xosc_lf clock. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change. |
9 | CLK_LOSS_EN | R/W | 0h | Enable clock loss detection and hence the indicators
to the system controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF
clock loss indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed. |
8-7 | ACLK_TDC_SRC_SEL | R/W | 0h | Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01: RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used |
6-4 | ACLK_REF_SRC_SEL | R/W | 0h | Source select for aclk_ref 000: RCOSC_HF derived (31.25kHz) 001: XOSC_HF derived (31.25kHz) 010: RCOSC_LF (32kHz) 011: XOSC_LF (32.768kHz) 100: RCOSC_MF (2MHz) 101-111: Not used |
3-2 | SCLK_LF_SRC_SEL | R/W | 0h | Source select for sclk_lf 0h = Low frequency clock derived from High Frequency RCOSC 1h = Low frequency clock derived from High Frequency XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN = 1) 2h = Low frequency RCOSC 3h = Low frequency XOSC |
1 | RESERVED | R | 0h | Reserved |
0 | SCLK_HF_SRC_SEL | R/W | 0h | Source select for sclk_hf. 0h = High frequency RCOSC clock 1h = High frequency XOSC or HPOSC clk (use HPOSC when HPOSC_MODE_EN = 1 |
CTL1 is shown in Table 7-107.
Return to the Summary Table.
Control 1
This register contains OSC_DIG configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-23 | RESERVED | R | 0h | Reserved |
22-18 | RCOSCHFCTRIMFRACT | R/W | 0h | Internal. Only to be used through TI provided API. |
17 | RCOSCHFCTRIMFRACT_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
16-10 | RESERVED | R | 0h | Reserved |
9 | FORCE_RCOSC_LF | R/W | 0h | Force rcosc_lf to be enabled 0: Disabled 1: Enabled |
8 | CLK_LF_LOSS_EN | R/W | 0h | Enable LF clock loss detection and hence the
indicators to the system controller. Checks SCLK_LF clock loss
indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed. |
7-2 | RESERVED | R | 0h | Reserved |
1-0 | XOSC_HF_FAST_START | R/W | 0h | Internal. Only to be used through TI provided API. |
RADCEXTCFG is shown in Table 7-108.
Return to the Summary Table.
RADC External Configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | HPM_IBIAS_WAIT_CNT | R/W | 0h | Internal. Only to be used through TI provided API. |
21-16 | LPM_IBIAS_WAIT_CNT | R/W | 0h | Internal. Only to be used through TI provided API. |
15-12 | IDAC_STEP | R/W | 0h | Internal. Only to be used through TI provided API. |
11-6 | RADC_DAC_TH | R/W | 0h | Internal. Only to be used through TI provided API. |
5 | RADC_MODE_IS_SAR | R/W | 0h | Internal. Only to be used through TI provided API. |
4-0 | RESERVED | R | 0h | Reserved |
AMPCOMPCTL is shown in Table 7-109.
Return to the Summary Table.
Amplitude Compensation Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R | 0h | Reserved |
30 | AMPCOMP_REQ_MODE | R/W | 0h | Internal. Only to be used through TI provided API. |
29-28 | AMPCOMP_FSM_UPDATE_RATE | R/W | 0h | Internal. Only to be used through TI provided API. |
27 | AMPCOMP_SW_CTRL | R/W | 0h | Internal. Only to be used through TI provided API. |
26 | AMPCOMP_SW_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
25-24 | RESERVED | R | 0h | Reserved |
23-20 | IBIAS_OFFSET | R/W | 0h | Internal. Only to be used through TI provided API. |
19-16 | IBIAS_INIT | R/W | 0h | Internal. Only to be used through TI provided API. |
15-8 | LPM_IBIAS_WAIT_CNT_FINAL | R/W | 0h | Internal. Only to be used through TI provided API. |
7-4 | CAP_STEP | R/W | 0h | Internal. Only to be used through TI provided API. |
3-0 | IBIASCAP_HPTOLP_OL_CNT | R/W | 0h | Internal. Only to be used through TI provided API. |
AMPCOMPTH1 is shown in Table 7-110.
Return to the Summary Table.
Amplitude Compensation Threshold 1
This register contains threshold values for amplitude compensation algorithm
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-18 | HPMRAMP3_LTH | R/W | 0h | Internal. Only to be used through TI provided API. |
17-16 | RESERVED | R | 0h | Reserved |
15-10 | HPMRAMP3_HTH | R/W | 0h | Internal. Only to be used through TI provided API. |
9-6 |
IBIASCAP_LPTOHP_ OL_CNT | R/W | 0h | Internal. Only to be used through TI provided API. |
5-0 | HPMRAMP1_TH | R/W | 0h | Internal. Only to be used through TI provided API. |
AMPCOMPTH2 is shown in Table 7-111.
Return to the Summary Table.
Amplitude Compensation Threshold 2
This register contains threshold values for amplitude compensation algorithm.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | LPMUPDATE_LTH | R/W | 0h | Internal. Only to be used through TI provided API. |
25-24 | RESERVED | R | 0h | Reserved |
23-18 | LPMUPDATE_HTH | R/W | 0h | Internal. Only to be used through TI provided API. |
17-16 | RESERVED | R | 0h | Reserved |
15-10 | ADC_COMP_AMPTH_LPM | R/W | 0h | Internal. Only to be used through TI provided API. |
9-8 | RESERVED | R | 0h | Reserved |
7-2 | ADC_COMP_AMPTH_HPM | R/W | 0h | Internal. Only to be used through TI provided API. |
1-0 | RESERVED | R | 0h | Reserved |
ANABYPASSVAL1 is shown in Table 7-112.
Return to the Summary Table.
Analog Bypass Values 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-20 | RESERVED | R | 0h | Reserved |
19-16 | XOSC_HF_ROW_Q12 | R/W | 0h | Internal. Only to be used through TI provided API. |
15-0 | XOSC_HF_COLUMN_Q12 | R/W | 0h | Internal. Only to be used through TI provided API. |
ANABYPASSVAL2 is shown in Table 7-113.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R | 0h | Reserved |
13-0 | XOSC_HF_IBIASTHERM | R/W | 0h | Internal. Only to be used through TI provided API. |
ATESTCTL is shown in Table 7-114.
Return to the Summary Table.
Analog Test Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | SCLK_LF_AUX_EN | R/W | 0h | Enable 32 kHz clock to AUX_COMPB. |
30-16 | RESERVED | R | 0h | Reserved |
15-14 | TEST_RCOSCMF | R/W | 0h | Test mode control for RCOSC_MF 0x0: test modes disabled 0x1: boosted bias current into self biased inverter 0x2: clock qualification disabled 0x3: boosted bias current into self biased inverter + clock qualification disabled |
13-12 | ATEST_RCOSCMF | R/W | 0h | ATEST control for RCOSC_MF 0x0: ATEST disabled 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock. 0x2: ATEST disabled 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* enabled to send out 2MHz clock. |
11-0 | RESERVED | R | 0h | Reserved |
ADCDOUBLERNANOAMPCTL is shown in Table 7-115.
Return to the Summary Table.
ADC Doubler Nanoamp Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | NANOAMP_BIAS_ENABLE | R/W | 0h | Internal. Only to be used through TI provided API. |
23 | SPARE23 | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior |
22-6 | RESERVED | R | 0h | Reserved |
5 | ADC_SH_MODE_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
4 | ADC_SH_VBUF_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
3-2 | RESERVED | R | 0h | Reserved |
1-0 | ADC_IREF_CTRL | R/W | 0h | Internal. Only to be used through TI provided API. |
XOSCHFCTL is shown in Table 7-116.
Return to the Summary Table.
XOSCHF Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R | 0h | Reserved |
13 |
TCXO_MODE_XOSC_ HF_EN | R/W | 0h | If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, turning on the XOSC_HF bias current allowing a DC bias point to be provided to the clipped-sine wave clock signal on external input. |
12 | TCXO_MODE | R/W | 0h | If this register is 1 when BYPASS is 1, this will enable clock qualification on the TCXO clock on external input. This register has no effect when BYPASS is 0. |
11-10 | RESERVED | R | 0h | Reserved |
9-8 | PEAK_DET_ITRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
7 | RESERVED | R | 0h | Reserved |
6 | BYPASS | R/W | 0h | Internal. Only to be used through TI provided API. |
5 | RESERVED | R | 0h | Reserved |
4-2 | HP_BUF_ITRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
1-0 | LP_BUF_ITRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
LFOSCCTL is shown in Table 7-117.
Return to the Summary Table.
Low Frequency Oscillator Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Reserved |
23-22 | XOSCLF_REGULATOR_TRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
21-18 | XOSCLF_CMIRRWR_RATIO | R/W | 0h | Internal. Only to be used through TI provided API. |
17-10 | RESERVED | R | 0h | Reserved |
9-8 | RCOSCLF_RTUNE_TRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
7-0 | RCOSCLF_CTUNE_TRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
RCOSCHFCTL is shown in Table 7-118.
Return to the Summary Table.
RCOSCHF Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-8 | RCOSCHF_CTRIM | R/W | 0h | Internal. Only to be used through TI provided API. |
7-0 | RESERVED | R | 0h | Reserved |
RCOSCMFCTL is shown in Table 7-119.
Return to the Summary Table.
RCOSC_MF Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-9 | RCOSC_MF_CAP_ARRAY | R/W | 0h | Adjust RCOSC_MF capacitor array. 0x0: nominal frequency, 0.625pF 0x40: highest frequency, 0.125pF 0x3F: lowest frequency, 1.125pF |
8 | RCOSC_MF_REG_SEL | R/W | 0h | Choose regulator type. 0: default 1: alternate |
7-6 | RCOSC_MF_RES_COARSE | R/W | 0h | Select coarse resistor for frequency adjustment. 0x0: 400kΩs, default 0x1: 300kΩs, min 0x2: 600kΩs, max 0x3: 500kΩs |
5-4 | RCOSC_MF_RES_FINE | R/W | 0h | Select fine resistor for frequency adjustment. 0x0: 11kΩs, minimum resistance, max freq 0x1: 13kΩs 0x2: 16kΩs 0x3: 20kΩs, max resistance, min freq |
3-0 | RCOSC_MF_BIAS_ADJ | R/W | 0h | Adjusts bias current to RCOSC_MF. The trim has binary
encoding with MSB inverted. 0x5 Minimum current 0x6 Default -10 0x7 Default -9 . . . 0xF Default -1 0x0 Default current 0x1 Default +1 0x2 Default +2 0x3 Default +3 0x4 Maximum current |
STAT0 is shown in Table 7-120.
Return to the Summary Table.
Status 0
This register contains status signals from OSC_DIG
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RCOSC_LF_GOOD | R | 0h | RCOSC_LF_GOOD |
30-29 | SCLK_LF_SRC | R | 0h | Indicates source for the sclk_lf 0h = Low frequency clock derived from High Frequency RCOSC 1h = Low frequency clock derived from High Frequency XOSC 2h = Low frequency RCOSC 3h = Low frequency XOSC |
28 | SCLK_HF_SRC | R | 0h | Indicates source for the sclk_hf 0h = High frequency RCOSC clock 1h = High frequency XOSC |
27-23 | RESERVED | R | 0h | Reserved |
22 | RCOSC_HF_EN | R | 0h | RCOSC_HF_EN |
21 | RCOSC_LF_EN | R | 0h | RCOSC_LF_EN |
20 | XOSC_LF_EN | R | 0h | XOSC_LF_EN |
19 | CLK_DCDC_RDY | R | 0h | CLK_DCDC_RDY |
18 | CLK_DCDC_RDY_ACK | R | 0h | CLK_DCDC_RDY_ACK |
17 | SCLK_HF_LOSS | R | 0h | Indicates sclk_hf is lost |
16 | SCLK_LF_LOSS | R | 0h | Indicates sclk_lf is lost |
15 | XOSC_HF_EN | R | 0h | Indicates that XOSC_HF is enabled. |
14 | RESERVED | R | 0h | Reserved |
13 | XB_48M_CLK_EN | R | 0h | Indicates that the 48MHz clock from the DOUBLER is
enabled. It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler bypass for the 48MHz crystal). |
12 | RESERVED | R | 0h | Reserved |
11 | XOSC_HF_LP_BUF_EN | R | 0h | XOSC_HF_LP_BUF_EN |
10 | XOSC_HF_HP_BUF_EN | R | 0h | XOSC_HF_HP_BUF_EN |
9 | RESERVED | R | 0h | Reserved |
8 | ADC_THMET | R | 0h | ADC_THMET |
7 | ADC_DATA_READY | R | 0h | indicates when adc_data is ready. |
6-1 | ADC_DATA | R | 0h | adc_data |
0 | PENDINGSCLKHFSWITCHING | R | 0h | Indicates when SCLK_HF clock source is ready to be switched |
STAT1 is shown in Table 7-121.
Return to the Summary Table.
Status 1
This register contains status signals from OSC_DIG
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RAMPSTATE | R | 0h | AMPCOMP FSM State
0h = RESET 1h = INITIALIZATION 2h = HPM_RAMP1 3h = HPM_RAMP2 4h = HPM_RAMP3 5h = HPM_UPDATE 6h = IDAC_INCREMENT 7h = IBIAS_CAP_UPDATE 8h = IBIAS_DECREMENT_WITH_MEASURE 9h = LPM_UPDATE Ah = IBIAS_INCREMENT Bh = IDAC_DECREMENT_WITH_MEASURE Ch = DUMMY_TO_INIT_1 Dh = FAST_START Eh = FAST_START_SETTLE |
27-22 | HPM_UPDATE_AMP | R | 0h | XOSC_HF amplitude during HPM_UPDATE state. When amplitude compensation of XOSC_HF is enabled in high performance mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value. |
21-16 | LPM_UPDATE_AMP | R | 0h | XOSC_HF amplitude during LPM_UPDATE state When amplitude compensation of XOSC_HF is enabled in low power mode, this value is the amplitude of the crystal oscillations measured by the on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 would indicate that the amplitude of the crystal is approximately 480 mV. To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero value. |
15 | FORCE_RCOSC_HF | R | 0h | force_rcosc_hf |
14 | SCLK_HF_EN | R | 0h | SCLK_HF_EN |
13 | SCLK_MF_EN | R | 0h | SCLK_MF_EN |
12 | ACLK_ADC_EN | R | 0h | ACLK_ADC_EN |
11 | ACLK_TDC_EN | R | 0h | ACLK_TDC_EN |
10 | ACLK_REF_EN | R | 0h | ACLK_REF_EN |
9 | CLK_CHP_EN | R | 0h | CLK_CHP_EN |
8 | CLK_DCDC_EN | R | 0h | CLK_DCDC_EN |
7 | SCLK_HF_GOOD | R | 0h | SCLK_HF_GOOD |
6 | SCLK_MF_GOOD | R | 0h | SCLK_MF_GOOD |
5 | SCLK_LF_GOOD | R | 0h | SCLK_LF_GOOD |
4 | ACLK_ADC_GOOD | R | 0h | ACLK_ADC_GOOD |
3 | ACLK_TDC_GOOD | R | 0h | ACLK_TDC_GOOD |
2 | ACLK_REF_GOOD | R | 0h | ACLK_REF_GOOD. |
1 | CLK_CHP_GOOD | R | 0h | CLK_CHP_GOOD |
0 | CLK_DCDC_GOOD | R | 0h | CLK_DCDC_GOOD |
STAT2 is shown in Table 7-122.
Return to the Summary Table.
Status 2
This register contains status signals from AMPCOMP FSM
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | ADC_DCBIAS | R | 0h | DC Bias read by RADC during SAR mode The value is an unsigned integer. It is used for debug only. |
25 | HPM_RAMP1_THMET | R | 0h | Indication of threshold is met for hpm_ramp1 |
24 | HPM_RAMP2_THMET | R | 0h | Indication of threshold is met for hpm_ramp2 |
23 | HPM_RAMP3_THMET | R | 0h | Indication of threshold is met for hpm_ramp3 |
22-16 | RESERVED | R | 0h | Reserved |
15-12 | RAMPSTATE | R | 0h | xosc_hf amplitude compensation FSM This is identical to STAT1.RAMPSTATE. See that description for encoding. |
11-4 | RESERVED | R | 0h | Reserved |
3 | AMPCOMP_REQ | R | 0h | ampcomp_req |
2 | XOSC_HF_AMPGOOD | R | 0h | amplitude of xosc_hf is within the required threshold (set by DDI). Not used for anything just for debug/status |
1 | XOSC_HF_FREQGOOD | R | 0h | frequency of xosc_hf is good to use for the digital clocks |
0 | XOSC_HF_RF_FREQGOOD | R | 0h | frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio operations. Used for SW to start synthesizer. |