SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-182 lists the memory-mapped registers for the CPU_FPU registers. All register offset addresses not listed in Table 2-182 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
4h | FPCCR | Holds control data for the Floating-point extension | Section 2.5.10.1 |
8h | FPCAR | Holds the location of the unpopulated floating-point register space allocated on an exception stack frame | Section 2.5.10.2 |
Ch | FPDSCR | Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context | Section 2.5.10.3 |
10h | MVFR0 | Describes the features provided by the Floating-point Extension | Section 2.5.10.4 |
14h | MVFR1 | Describes the features provided by the Floating-point Extension | Section 2.5.10.5 |
18h | MVFR2 | Describes the features provided by the Floating-point Extension | Section 2.5.10.6 |
Complex bit access types are encoded to fit into small table cells. Table 2-183 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
FPCCR is shown in Table 2-184.
Return to the Summary Table.
Holds control data for the Floating-point extension
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ASPEN | R/W | 0h | When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1 |
30 | LSPEN | R/W | 0h | Enables lazy context save of floating-point state |
29 | LSPENS | R/W | 0h | This bit controls whether the LSPEN bit is writeable from the Non-secure state |
28 | CLRONRET | R/W | 0h | Clear floating-point caller saved registers on exception return |
27 | CLRONRETS | R/W | 0h | This bit controls whether the CLRONRET bit is writeable from the Non-secure state |
26 | TS | R/W | 0h | Treat floating-point registers as Secure enable |
25-11 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
10 | UFRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending |
9 | SPLIMVIOL | R/W | 0h | This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior |
8 | MONRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending |
7 | SFRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state |
6 | BFRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending |
5 | MMRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending |
4 | HFRDY | R/W | 0h | Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending |
3 | THREAD | R/W | 0h | Indicates the PE mode when it allocated the floating-point stack frame |
2 | S | R/W | 0h | Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed |
1 | USER | R/W | 0h | Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame |
0 | LSPACT | R/W | 0h | Indicates whether lazy preservation of the floating-point state is active |
FPCAR is shown in Table 2-185.
Return to the Summary Table.
Holds the location of the unpopulated floating-point register space allocated on an exception stack frame
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | ADDRESS | R/W | 0h | The location of the unpopulated floating-point register space allocated on an exception stack frame |
2-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
FPDSCR is shown in Table 2-186.
Return to the Summary Table.
Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-27 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
26 | AHP | R/W | 0h | Default value for FPSCR.AHP |
25 | DN | R/W | 0h | Default value for FPSCR.DN |
24 | FZ | R/W | 0h | Default value for FPSCR.FZ |
23-22 | RMode | R/W | 0h | Default value for FPSCR.RMode |
21-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
MVFR0 is shown in Table 2-187.
Return to the Summary Table.
Describes the features provided by the Floating-point Extension
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | FPRound | R | 0h | Indicates the rounding modes supported by the FP Extension |
27-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
23-20 | FPSqrt | R | 0h | Indicates the support for FP square root operations |
19-16 | FPDivide | R | 0h | Indicates the support for FP divide operations |
15-12 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
11-8 | FPDP | R | 0h | Indicates support for FP double-precision operations |
7-4 | FPSP | R | 0h | Indicates support for FP single-precision operations |
3-0 | SIMDReg | R | 0h | Indicates size of FP register file |
MVFR1 is shown in Table 2-188.
Return to the Summary Table.
Describes the features provided by the Floating-point Extension
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | FMAC | R | 0h | Indicates whether the FP Extension implements the fused multiply accumulate instructions |
27-24 | FPHP | R | 0h | Indicates whether the FP Extension implements half-precision FP conversion instructions |
23-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | FPDNaN | R | 0h | Indicates whether the FP hardware implementation supports NaN propagation |
3-0 | FPFtZ | R | 0h | Indicates whether subnormals are always flushed-to-zero |
MVFR2 is shown in Table 2-189.
Return to the Summary Table.
Describes the features provided by the Floating-point Extension
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | FPMisc | R | 0h | Indicates support for miscellaneous FP features |
3-0 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |