SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 19-1 lists the memory-mapped registers for the WDT registers. All register offset addresses not listed in Table 19-1 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | LOAD | Configuration | Section 19.4.1 |
4h | VALUE | Current Count Value | Section 19.4.2 |
8h | CTL | Control | Section 19.4.3 |
Ch | ICR | Interrupt Clear | Section 19.4.4 |
10h | RIS | Raw Interrupt Status | Section 19.4.5 |
14h | MIS | Masked Interrupt Status | Section 19.4.6 |
418h | TEST | Test Mode | Section 19.4.7 |
41Ch | INT_CAUS | Interrupt Cause Test Mode | Section 19.4.8 |
C00h | LOCK | Lock | Section 19.4.9 |
Complex bit access types are encoded to fit into small table cells. Table 19-2 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
LOAD is shown in Table 19-3.
Return to the Summary Table.
Configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTLOAD | R/W | FFFFFFFFh | This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter is restarted to count down from the new value. If this register is loaded with 0x0000.0000, an interrupt is immediately generated. |
VALUE is shown in Table 19-4.
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Current Count Value
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTVALUE | R | FFFFFFFFh | This register contains the current count value of the timer. |
CTL is shown in Table 19-5.
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Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | INTTYPE | R/W | 0h | WDT Interrupt Type 0: WDT interrupt is a standard interrupt. 1: WDT interrupt is a non-maskable interrupt. |
1 | RESEN | R/W | 0h | WDT Reset Enable. Defines the function of the WDT reset source (see
PRCM:WARMRESET.WDT_STAT if enabled) 0: Disabled. 1: Enable the Watchdog reset output. |
0 | INTEN | R/W | 0h | WDT Interrupt Enable 0: Interrupt event disabled. 1: Interrupt event enabled. Once set, this bit can only be cleared by a hardware reset. |
ICR is shown in Table 19-6.
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Interrupt Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTICR | W | 0h | This register is the interrupt clear register. A write of any value to this register clears the WDT interrupt and reloads the 32-bit counter from the LOAD register. |
RIS is shown in Table 19-7.
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Raw Interrupt Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | WDTRIS | R | 0h | This register is the raw interrupt status register. WDT interrupt events can be monitored via this register if the controller interrupt is masked. Value Description 0: The WDT has not timed out 1: A WDT time-out event has occurred |
MIS is shown in Table 19-8.
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Masked Interrupt Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | WDTMIS | R | 0h | This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the WDT interrupt enable bit CTL.INTEN. Value Description 0: The WDT has not timed out or is masked. 1: An unmasked WDT time-out event has occurred. |
TEST is shown in Table 19-9.
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Test Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | STALL | R/W | 0h | WDT Stall Enable 0: The WDT timer continues counting if the CPU is stopped with a debugger. 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the CPU is restarted, the WDT resumes counting. |
7-1 | RESERVED | R | 0h | Reserved |
0 | TEST_EN | R/W | 0h | The test enable bit 0: Enable external reset 1: Disables the generation of an external reset. Instead bit 1 of the INT_CAUS register is set and an interrupt is generated |
INT_CAUS is shown in Table 19-10.
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Interrupt Cause Test Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | CAUSE_RESET | R | 0h | Indicates that the cause of an interrupt was a reset generated but blocked due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). |
0 | CAUSE_INTR | R | 0h | Replica of RIS.WDTRIS |
LOCK is shown in Table 19-11.
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Lock
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | WDTLOCK | R/W | 0h | WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates (NOTE: TEST.TEST_EN bit is not lockable). A read of this register returns the following values: 0x0000.0000: Unlocked 0x0000.0001: Locked |