SWCU194 March   2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1 Target Applications
    2. 1.2 Overview
    3. 1.3 Functional Overview
      1. 1.3.1  ArmCortex-M33 with FPU
        1. 1.3.1.1 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block (SCB)
      2. 1.3.2  On-Chip Memory
        1. 1.3.2.1 SRAM
        2. 1.3.2.2 Flash Memory
        3. 1.3.2.3 ROM
      3. 1.3.3  Radio
      4. 1.3.4  Security Core
      5. 1.3.5  Runtime Security
      6. 1.3.6  General-Purpose Timers
        1. 1.3.6.1 Watchdog Timer
        2. 1.3.6.2 Always-On Domain
      7. 1.3.7  Direct Memory Access
      8. 1.3.8  System Control and Clock
      9. 1.3.9  Serial Communication Peripherals
        1. 1.3.9.1 UART
        2. 1.3.9.2 I2C
        3. 1.3.9.3 I2S
        4. 1.3.9.4 SPI
      10. 1.3.10 Programmable I/Os
      11. 1.3.11 Sensor Controller
      12. 1.3.12 Random Number Generator
      13. 1.3.13 cJTAG and JTAG
      14. 1.3.14 Power Supply System
        1. 1.3.14.1 Supply System
          1. 1.3.14.1.1 VDDS
          2. 1.3.14.1.2 VDDR
          3. 1.3.14.1.3 Digital Core Supply
          4. 1.3.14.1.4 Other Internal Supplies
        2. 1.3.14.2 DC/DC Converter
  3. 2  Arm Cortex-M33 Processor with FPU
    1. 2.1 Arm Cortex-M33 Processor Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Integrated Configurable Debug
      2. 2.3.2 Trace Port Interface Unit
      3. 2.3.3 Arm Cortex-M33 System Peripheral Details
        1. 2.3.3.1 Floating Point Unit (FPU)
        2. 2.3.3.2 Memory Protection Unit (MPU)
        3. 2.3.3.3 System Timer (SysTick)
        4. 2.3.3.4 Nested Vectored Interrupt Controller (NVIC)
        5. 2.3.3.5 System Control Block (SCB)
        6. 2.3.3.6 System Control Space (SCS)
        7. 2.3.3.7 Security Attribution Unit (SAU)
    4. 2.4 Programming Model
      1. 2.4.1 Modes of Operation and Execution
        1. 2.4.1.1 Security States
        2. 2.4.1.2 Operating Modes
        3. 2.4.1.3 Operating States
        4. 2.4.1.4 Privileged Access and Unprivileged User Access
      2. 2.4.2 Instruction Set Summary
      3. 2.4.3 Memory Model
        1. 2.4.3.1 Private Peripheral Bus
        2. 2.4.3.2 Unaligned Accesses
      4. 2.4.4 Exclusive Monitor
      5. 2.4.5 Processor Core Registers Summary
      6. 2.4.6 Exceptions
        1. 2.4.6.1 Exception Handling and Prioritization
      7. 2.4.7 Runtime Security
        1. 2.4.7.1 IDAU Watermark Registers
        2. 2.4.7.2 Secure Memory Range for Registers
        3. 2.4.7.3 Bus Topology
        4. 2.4.7.4 Intended Use
    5. 2.5 Arm® Cortex®-M33 Registers
      1. 2.5.1  CPU_ITM Registers
      2. 2.5.2  CPU_DWT Registers
      3. 2.5.3  CPU_SYSTICK Registers
      4. 2.5.4  CPU_NVIC Registers
      5. 2.5.5  CPU_SCS Registers
      6. 2.5.6  CPU_MPU Registers
      7. 2.5.7  CPU_SAU Registers
      8. 2.5.8  CPU_DCB Registers
      9. 2.5.9  CPU_SIG Registers
      10. 2.5.10 CPU_FPU Registers
      11. 2.5.11 CPU_TPIU Registers
  4. 3 Memory Map
    1. 3.1 Introduction
    2. 3.2 Memory Map (Secure and Non-secure)
      1. 3.2.1 Bus Security
    3. 3.3 Memory Map
  5. 4  Arm Cortex-M33 Peripherals
    1. 4.1 Arm Cortex-M33 Peripherals Introduction
  6. 5 Interrupts and Events
    1. 5.1 Exception Model
      1. 5.1.1 Exception States
      2. 5.1.2 Exception Types
      3. 5.1.3 Exception Handlers
      4. 5.1.4 Vector Table
      5. 5.1.5 Exception Priorities
      6. 5.1.6 Interrupt Priority Grouping
      7. 5.1.7 Exception Entry and Return
        1. 5.1.7.1 Exception Entry
        2. 5.1.7.2 Exception Return
    2. 5.2 Fault Handling
      1. 5.2.1 Fault Types
      2. 5.2.2 Fault Escalation and Hard Faults
      3. 5.2.3 Fault Status Registers and Fault Address Registers
      4. 5.2.4 Lockup
    3. 5.3 Security State Switches
    4. 5.4 Event Fabric
      1. 5.4.1 Introduction
      2. 5.4.2 Event Fabric Overview
        1. 5.4.2.1 Registers
    5. 5.5 AON Event Fabric
      1. 5.5.1 Common Input Event List
      2. 5.5.2 Event Subscribers
        1. 5.5.2.1 AON Power Management Controller (AON_PMCTL)
        2. 5.5.2.2 Real-Time Clock
        3. 5.5.2.3 MCU Event Fabric
    6. 5.6 MCU Event Fabric
      1. 5.6.1 Common Input Event List
      2. 5.6.2 Event Subscribers
        1. 5.6.2.1 System CPU
        2. 5.6.2.2 NMI
        3. 5.6.2.3 Freeze
    7. 5.7 AON Events
    8. 5.8 Interrupts and Events Registers
      1. 5.8.1 AON_EVENT Registers
      2. 5.8.2 EVENT Registers
  7. 6 JTAG Interface
    1. 6.1 Overview
    2. 6.2 cJTAG
    3. 6.3 ICEPick
      1. 6.3.1 Secondary TAPs
        1. 6.3.1.1 Slave DAP (CPU DAP)
      2. 6.3.2 ICEPick Registers
        1. 6.3.2.1 IR Instructions
        2. 6.3.2.2 Data Shift Register
        3. 6.3.2.3 Instruction Register
        4. 6.3.2.4 Bypass Register
        5. 6.3.2.5 Device Identification Register
        6. 6.3.2.6 User Code Register
        7. 6.3.2.7 ICEPick Identification Register
        8. 6.3.2.8 Connect Register
      3. 6.3.3 Router Scan Chain
      4. 6.3.4 TAP Routing Registers
        1. 6.3.4.1 ICEPick Control Block
          1. 6.3.4.1.1 All0s Register
          2. 6.3.4.1.2 ICEPick Control Register
          3. 6.3.4.1.3 Linking Mode Register
        2. 6.3.4.2 Test TAP Linking Block
          1. 6.3.4.2.1 Secondary Test TAP Register
        3. 6.3.4.3 Debug TAP Linking Block
          1. 6.3.4.3.1 Secondary Debug TAP Register
    4. 6.4 ICEMelter
    5. 6.5 Serial Wire Viewer (SWV)
    6. 6.6 Halt In Boot (HIB)
    7. 6.7 Debug and Shutdown
    8. 6.8 Boundary Scan
  8. 7 Power, Reset, and Clock Management (PRCM)
    1. 7.1 Introduction
    2. 7.2 System CPU Mode
    3. 7.3 Supply System
      1. 7.3.1 Internal DC/DC Converter and Global LDO
      2. 7.3.2 External Regulator Mode
    4. 7.4 Digital Power Partitioning
      1. 7.4.1 MCU_VD
        1. 7.4.1.1 MCU_VD Power Domains
      2. 7.4.2 AON_VD
        1. 7.4.2.1 AON_VD Power Domains
    5. 7.5 Clock Management
      1. 7.5.1 System Clocks
        1. 7.5.1.1 Controlling the Oscillators
      2. 7.5.2 Clocks in MCU_VD
        1. 7.5.2.1 Clock Gating
        2. 7.5.2.2 Scaler to GPTs
        3. 7.5.2.3 Scaler to WDT
      3. 7.5.3 Clocks in AON_VD
    6. 7.6 Power Modes
      1. 7.6.1 Start-Up State
      2. 7.6.2 Active Mode
      3. 7.6.3 Idle Mode
      4. 7.6.4 Standby Mode
      5. 7.6.5 Shutdown Mode
    7. 7.7 Reset
      1. 7.7.1 System Resets
        1. 7.7.1.1 Clock Loss Detection
        2. 7.7.1.2 Software-Initiated System Reset
        3. 7.7.1.3 Warm Reset Converted to System Reset
      2. 7.7.2 Reset of the MCU_VD Power Domains and Modules
      3. 7.7.3 Reset of AON_VD
      4. 7.7.4 Always On Watchdog Timer (AON_WDT)
    8. 7.8 PRCM Registers
      1. 7.8.1 PRCM Registers
      2. 7.8.2 AON_PMCTL Registers
      3. 7.8.3 DDI_0_OSC Registers
  9. 8 Versatile Instruction Memory System (VIMS)
    1. 8.1 Introduction
    2. 8.2 VIMS Configurations
      1. 8.2.1 VIMS Modes
        1. 8.2.1.1 GPRAM Mode
        2. 8.2.1.2 Off Mode
        3. 8.2.1.3 Cache Mode
      2. 8.2.2 VIMS FLASH Line Buffers
      3. 8.2.3 VIMS Arbitration
      4. 8.2.4 VIMS Cache TAG Prefetch
    3. 8.3 VIMS Software Remarks
      1. 8.3.1 FLASH Program or Update
      2. 8.3.2 VIMS Retention
        1. 8.3.2.1 Mode 1
        2. 8.3.2.2 Mode 2
        3. 8.3.2.3 Mode 3
    4. 8.4 FLASH
      1. 8.4.1 Flash Memory Protection
      2. 8.4.2 Flash Memory Programming
    5. 8.5 ROM Functions
    6. 8.6 VIMS Registers
      1. 8.6.1 FLASH Registers
      2. 8.6.2 VIMS Registers
      3. 8.6.3 NVMNW Registers
  10. 9 SRAM
    1. 9.1 Introduction
    2. 9.2 Main Features
    3. 9.3 Data Retention
    4. 9.4 Parity and SRAM Error Support
      1. 9.4.1 SRAM Extension Mode
    5. 9.5 SRAM Auto-Initialization
    6. 9.6 Parity Debug Behavior
    7. 9.7 SRAM Registers
      1. 9.7.1 SRAM_MMR Registers
      2. 9.7.2 SRAM Registers
  11. 10Bootloader
    1. 10.1 Bootloader Functionality
      1. 10.1.1 Bootloader Disabling
      2. 10.1.2 Bootloader Backdoor
    2. 10.2 Bootloader Interfaces
      1. 10.2.1 Packet Handling
        1. 10.2.1.1 Packet Acknowledge and Not-Acknowledge Bytes
      2. 10.2.2 Transport Layer
        1. 10.2.2.1 UART Transport
          1. 10.2.2.1.1 UART Baud Rate Automatic Detection
        2. 10.2.2.2 SPI Transport
      3. 10.2.3 Serial Bus Commands
        1. 10.2.3.1  COMMAND_PING
        2. 10.2.3.2  COMMAND_DOWNLOAD
        3. 10.2.3.3  COMMAND_GET_STATUS
        4. 10.2.3.4  COMMAND_SEND_DATA
        5. 10.2.3.5  COMMAND_RESET
        6. 10.2.3.6  COMMAND_SECTOR_ERASE
        7. 10.2.3.7  COMMAND_CRC32
        8. 10.2.3.8  COMMAND_GET_CHIP_ID
        9. 10.2.3.9  COMMAND_MEMORY_READ
        10. 10.2.3.10 COMMAND_MEMORY_WRITE
        11. 10.2.3.11 COMMAND_BANK_ERASE
        12. 10.2.3.12 COMMAND_SET_CCFG
        13. 10.2.3.13 COMMAND_DOWNLOAD_CRC
  12. 11Device Configuration
    1. 11.1 Customer Configuration (CCFG)
      1. 11.1.1 CCFG Recommendations for Final Production
    2. 11.2 CCFG Registers
    3. 11.3 Factory Configuration (FCFG)
    4. 11.4 FCFG1 Registers
  13. 12AES and Hash Cryptoprocessor
    1. 12.1 Introduction
    2. 12.2 Functional Description
      1. 12.2.1 Debug Capabilities
      2. 12.2.2 Exception Handling
      3. 12.2.3 Power Management and Sleep Modes
      4. 12.2.4 Interrupts
      5. 12.2.5 Module Memory Map
      6. 12.2.6 Master Control and Select Module
        1. 12.2.6.1 Algorithm Select Register
          1. 12.2.6.1.1 Algorithm Select
        2. 12.2.6.2 Master PROT Enable
          1. 12.2.6.2.1 Master PROT-Privileged Access-Enable
        3. 12.2.6.3 Software Reset
      7. 12.2.7 AES Engine
        1. 12.2.7.1 Second and Third Key Registers (Internal, but Clearable)
        2. 12.2.7.2 AES Initialization Vector (IV) Registers
        3. 12.2.7.3 AES I/O Buffer Control, Mode, and Length Registers
        4. 12.2.7.4 AES Data Input and Output Registers
        5. 12.2.7.5 TAG Registers
      8. 12.2.8 Key Area Registers
        1. 12.2.8.1 Key Store Write Area Register
        2. 12.2.8.2 Key Store Written Area Register
        3. 12.2.8.3 Key Store Size Register
        4. 12.2.8.4 Key Store Read Area Register
      9. 12.2.9 Hash Engine
        1. 12.2.9.1 Hash I/O Buffer Control and Status Register, Mode, and Length Registers
        2. 12.2.9.2 Hash Data Input and Digest Registers
    3. 12.3 DMA Controller
      1. 12.3.1 Internal Operation
      2. 12.3.2 Supported DMA Operations
    4. 12.4 AES and Hash Cryptoprocessor Performance
      1. 12.4.1 Introduction
      2. 12.4.2 Performance for DMA-Based Operations
    5. 12.5 Programming Guidelines
      1. 12.5.1 One-Time Initialization After a Reset
      2. 12.5.2 DMAC and Master Control
        1. 12.5.2.1 Regular Use
        2. 12.5.2.2 Interrupting DMA Transfers
        3. 12.5.2.3 Interrupts, Hardware, and Software Synchronization
      3. 12.5.3 Hashing
        1. 12.5.3.1 Data Format and Byte Order
        2. 12.5.3.2 Basic Hash with Data From DMA
          1. 12.5.3.2.1 New Hash Session with Digest Read Through Slave
          2. 12.5.3.2.2 New Hash Session with Digest to External Memory
          3. 12.5.3.2.3 Resumed Hash Session
        3. 12.5.3.3 HMAC
          1. 12.5.3.3.1 Secure HMAC
        4. 12.5.3.4 Alternative Basic Hash Where Data Originates from Slave Interface
          1. 12.5.3.4.1 New Hash Session
          2. 12.5.3.4.2 Resumed Hash Session
      4. 12.5.4 Encryption and Decryption
        1. 12.5.4.1 Data Format and Byte Order
        2. 12.5.4.2 Key Store
          1. 12.5.4.2.1 Load Keys from External Memory
        3. 12.5.4.3 Basic AES Modes
          1. 12.5.4.3.1 AES-ECB
          2. 12.5.4.3.2 AES-CBC
          3. 12.5.4.3.3 AES-CTR
          4. 12.5.4.3.4 Programming Sequence with DMA Data
        4. 12.5.4.4 CBC-MAC
          1. 12.5.4.4.1 Programming Sequence for Regular CBC-MAC
          2. 12.5.4.4.2 Programming Sequence for Regular CBC-MAC with Continuation
          3. 12.5.4.4.3 Programming Sequence for CMAC CBC-MAC
          4. 12.5.4.4.4 Programming Sequence for CMAC CBC-MAC with Continuation
        5. 12.5.4.5 AES-CCM
          1. 12.5.4.5.1 Continued CCM Processing
          2. 12.5.4.5.2 Programming Sequence for AES-CCM
          3. 12.5.4.5.3 Programming Sequence for Continued AES-CCM in the AAD Phase
          4. 12.5.4.5.4 Programming Sequence for Continued AES-CCM in the Payload Phase
        6. 12.5.4.6 AES-GCM
          1. 12.5.4.6.1 Continued AES-GCM Processing
          2. 12.5.4.6.2 Programming Sequence for AES-GCM
          3. 12.5.4.6.3 Programming Sequence for Continued AES-GCM in the AAD Phase
          4. 12.5.4.6.4 Programming Sequence for Continued AES-GCM in the Payload Phase
      5. 12.5.5 Exceptions Handling
        1. 12.5.5.1 Soft Reset
        2. 12.5.5.2 External Port Errors
        3. 12.5.5.3 Key Store Errors
    6. 12.6 Conventions and Compliances
      1. 12.6.1 Conventions Used in This Manual
        1. 12.6.1.1 Terminology
        2. 12.6.1.2 Formulas and Nomenclature
      2. 12.6.2 Compliance
    7. 12.7 CRYPTO Registers
  14. 13PKA Engine
    1. 13.1 Introduction
    2. 13.2 Functional Description
      1. 13.2.1 Module Architecture
      2. 13.2.2 PKA RAM
      3. 13.2.3 PKCP Operations
      4. 13.2.4 Sequencer Operations
        1. 13.2.4.1 Modular Exponentiation Operations
        2. 13.2.4.2 Modular Inversion Operation
        3. 13.2.4.3 ECC Operations
      5. 13.2.5 Operation Sequence
    3. 13.3 PKA Engine Performance
      1. 13.3.1 Basic Operations Performance
      2. 13.3.2 ExpMod Performance
      3. 13.3.3 Modular Inversion Performance
      4. 13.3.4 ECC Operation Performance
    4. 13.4 PKA Registers
  15. 14True Random Number Generator (TRNG)
    1. 14.1 Introduction
    2. 14.2 Block Diagram
    3. 14.3 TRNG Software Reset
    4. 14.4 Interrupt Requests
    5. 14.5 TRNG Operation Description
      1. 14.5.1 TRNG Shutdown
      2. 14.5.2 TRNG Alarms
      3. 14.5.3 TRNG Entropy
    6. 14.6 TRNG Low-Level Programming Guide
      1. 14.6.1 Initialization
        1. 14.6.1.1 Interfacing Modules
        2. 14.6.1.2 TRNG Main Sequence
        3. 14.6.1.3 TRNG Operating Modes
          1. 14.6.1.3.1 Polling Mode
          2. 14.6.1.3.2 Interrupt Mode
    7. 14.7 TRNG Registers
  16. 15I/O Controller (IOC)
    1. 15.1  Introduction
    2. 15.2  IOC Overview
    3. 15.3  I/O Mapping and Configuration
      1. 15.3.1 Basic I/O Mapping
      2. 15.3.2 Mapping AUXIOs to DIO Pins
      3. 15.3.3 Control External LNA/PA (Range Extender) with I/Os
      4. 15.3.4 Map the 32 kHz System Clock (SCLK_LF Clock) to DIO
    4. 15.4  Edge Detection on DIO Pins
      1. 15.4.1 Configure DIO as GPIO Input to Generate Interrupt on Edge Detect
    5. 15.5  Unused I/O Pins
    6. 15.6  GPIO
    7. 15.7  I/O Pin Capability
    8. 15.8  Peripheral PORT_IDs
    9. 15.9  I/O Pins
      1. 15.9.1 Input/Output Modes
        1. 15.9.1.1 Physical Pin
        2. 15.9.1.2 Pin Configuration
    10. 15.10 IOC Registers
      1. 15.10.1 AON_IOC Registers
      2. 15.10.2 GPIO Registers
      3. 15.10.3 IOC Registers
  17. 16Micro Direct Memory Access (µDMA)
    1. 16.1 Introduction
    2. 16.2 Block Diagram
    3. 16.3 Functional Description
      1. 16.3.1  Channel Assignments
      2. 16.3.2  Priority
      3. 16.3.3  Arbitration Size
      4. 16.3.4  Request Types
        1. 16.3.4.1 Single Request
        2. 16.3.4.2 Burst Request
      5. 16.3.5  Channel Configuration
      6. 16.3.6  Transfer Modes
        1. 16.3.6.1 Stop Mode
        2. 16.3.6.2 Basic Mode
        3. 16.3.6.3 Auto Mode
        4. 16.3.6.4 Ping-Pong Mode
        5. 16.3.6.5 Memory Scatter-Gather Mode
        6. 16.3.6.6 Peripheral Scatter-Gather Mode
      7. 16.3.7  Transfer Size and Increments
      8. 16.3.8  Peripheral Interface
      9. 16.3.9  Software Request
      10. 16.3.10 Interrupts and Errors
    4. 16.4 Initialization and Configuration
      1. 16.4.1 Module Initialization
      2. 16.4.2 Configuring a Memory-to-Memory Transfer
        1. 16.4.2.1 Configure the Channel Attributes
        2. 16.4.2.2 Configure the Channel Control Structure
        3. 16.4.2.3 Start the Transfer
    5. 16.5 UDMA Registers
  18. 17Timers
    1. 17.1 Introduction
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1 GPTM Reset Conditions
      2. 17.3.2 Timer Modes
        1. 17.3.2.1 One-Shot or Periodic Timer Mode
        2. 17.3.2.2 Input Edge-Count Mode
        3. 17.3.2.3 Input Edge-Time Mode
        4. 17.3.2.4 PWM Mode
        5. 17.3.2.5 Wait-for-Trigger Mode
      3. 17.3.3 Synchronizing GPT Blocks
      4. 17.3.4 Accessing Concatenated 16- and 32-Bit GPTM Register Values
    4. 17.4 Initialization and Configuration
      1. 17.4.1 One-Shot and Periodic Timer Modes
      2. 17.4.2 Input Edge-Count Mode
      3. 17.4.3 Input Edge-Timing Mode
      4. 17.4.4 PWM Mode
      5. 17.4.5 Producing DMA Trigger Events
    5. 17.5 GPT Registers
  19. 18Real-Time Clock (RTC)
    1. 18.1 Introduction
    2. 18.2 Functional Specifications
      1. 18.2.1 Functional Overview
      2. 18.2.2 Free-Running Counter
      3. 18.2.3 Channels
        1. 18.2.3.1 Capture and Compare
      4. 18.2.4 Events
    3. 18.3 RTC Register Information
      1. 18.3.1 Register Access
      2. 18.3.2 Entering Sleep and Wakeup From Sleep
      3. 18.3.3 AON_RTC:SYNC Register
    4. 18.4 RTC Registers
      1. 18.4.1 AON_RTC Registers
  20. 19Watchdog Timer (WDT)
    1. 19.1 Introduction
    2. 19.2 Functional Description
    3. 19.3 Initialization and Configuration
    4. 19.4 WDT Registers
  21. 20AUX Domain Sensor Controller and Peripherals
    1. 20.1 Introduction
      1. 20.1.1 AUX Block Diagram
    2. 20.2 Power and Clock Management
      1. 20.2.1 Operational Modes
        1. 20.2.1.1 Dual-Rate AUX Clock
      2. 20.2.2 Use Scenarios
        1. 20.2.2.1 MCU
        2. 20.2.2.2 Sensor Controller
      3. 20.2.3 SCE Clock Emulation
      4. 20.2.4 AUX RAM Retention
    3. 20.3 Sensor Controller
      1. 20.3.1 Sensor Controller Studio
        1. 20.3.1.1 Programming Model
        2. 20.3.1.2 Task Development
        3. 20.3.1.3 Task Testing, Task Debugging and Run-Time Logging
        4. 20.3.1.4 Documentation
      2. 20.3.2 Sensor Controller Engine (SCE)
        1. 20.3.2.1  Registers
          1.        Pipeline Hazards
        2. 20.3.2.2  Memory Architecture
          1.        Memory Access to Instructions and Data
          2.        I/O Access to Module Registers
        3. 20.3.2.3  Program Flow
          1.        Zero-Overhead Loop
        4. 20.3.2.4  Instruction Set
          1. 20.3.2.4.1 Instruction Timing
          2. 20.3.2.4.2 Instruction Prefix
          3. 20.3.2.4.3 Instructions
        5. 20.3.2.5  SCE Event Interface
        6. 20.3.2.6  Math Accelerator (MAC)
        7. 20.3.2.7  Programmable Microsecond Delay
        8. 20.3.2.8  Wake-Up Event Handling
        9. 20.3.2.9  Access to AON Domain Registers
        10. 20.3.2.10 VDDR Recharge
    4. 20.4 Digital Peripheral Modules
      1. 20.4.1 Overview
        1. 20.4.1.1 DDI Control-Configuration
      2. 20.4.2 Analog I/O Digital I/O (AIODIO)
        1. 20.4.2.1 Introduction
        2. 20.4.2.2 Functional Description
          1. 20.4.2.2.1 Mapping to DIO Pins
          2. 20.4.2.2.2 Configuration
          3. 20.4.2.2.3 GPIO Mode
          4. 20.4.2.2.4 Input Buffer
          5. 20.4.2.2.5 Data Output Source
      3. 20.4.3 Semaphore (SMPH)
        1. 20.4.3.1 Introduction
        2. 20.4.3.2 Functional Description
        3. 20.4.3.3 Semaphore Allocation in TI Software
      4. 20.4.4 SPI Master (SPIM)
        1. 20.4.4.1 Introduction
        2. 20.4.4.2 Functional Description
          1. 20.4.4.2.1 TX and RX Operations
          2. 20.4.4.2.2 Configuration
          3. 20.4.4.2.3 Timing Diagrams
      5. 20.4.5 Time-to-Digital Converter (TDC)
        1. 20.4.5.1 Introduction
        2. 20.4.5.2 Functional Description
          1. 20.4.5.2.1 Command
          2. 20.4.5.2.2 Conversion Time Configuration
          3. 20.4.5.2.3 Status and Result
          4. 20.4.5.2.4 Clock Source Selection
            1. 20.4.5.2.4.1 Counter Clock
            2. 20.4.5.2.4.2 Reference Clock
          5. 20.4.5.2.5 Start and Stop Events
          6. 20.4.5.2.6 Prescaler
        3. 20.4.5.3 Supported Measurement Types
          1. 20.4.5.3.1 Measure Pulse Width
          2. 20.4.5.3.2 Measure Frequency
          3. 20.4.5.3.3 Measure Time Between Edges of Different Events Sources
            1. 20.4.5.3.3.1 Asynchronous Counter Start – Ignore 0 Stop Events
            2. 20.4.5.3.3.2 Synchronous Counter Start – Ignore 0 Stop Events
            3. 20.4.5.3.3.3 Asynchronous Counter Start – Ignore Stop Events
            4. 20.4.5.3.3.4 Synchronous Counter Start – Ignore Stop Events
          4. 20.4.5.3.4 Pulse Counting
      6. 20.4.6 Timer01
        1. 20.4.6.1 Introduction
        2. 20.4.6.2 Functional Description
      7. 20.4.7 Timer2
        1. 20.4.7.1 Introduction
        2. 20.4.7.2 Functional Description
          1. 20.4.7.2.1 Clock Source
          2. 20.4.7.2.2 Clock Prescaler
          3. 20.4.7.2.3 Counter
          4. 20.4.7.2.4 Event Outputs
          5. 20.4.7.2.5 Channel Actions
            1. 20.4.7.2.5.1 Period and Pulse Width Measurement
            2. 20.4.7.2.5.2 Clear on Zero, Toggle on Compare Repeatedly
            3. 20.4.7.2.5.3 Set on Zero, Toggle on Compare Repeatedly
          6. 20.4.7.2.6 Asynchronous Bus Bridge
    5. 20.5 Analog Peripheral Modules
      1. 20.5.1 Overview
        1. 20.5.1.1 ADI Control-Configuration
        2. 20.5.1.2 Block Diagram
      2. 20.5.2 Analog-to-Digital Converter (ADC)
        1. 20.5.2.1 Introduction
        2. 20.5.2.2 Functional Description
          1. 20.5.2.2.1 Input Selection and Scaling
          2. 20.5.2.2.2 Reference Selection
          3. 20.5.2.2.3 ADC Sample Mode
          4. 20.5.2.2.4 ADC Clock Source
          5. 20.5.2.2.5 ADC Trigger
          6. 20.5.2.2.6 Sample FIFO
          7. 20.5.2.2.7 µDMA Interface
          8. 20.5.2.2.8 Resource Ownership and Usage
      3. 20.5.3 Comparator A (COMPA)
        1. 20.5.3.1 Introduction
        2. 20.5.3.2 Functional Description
          1. 20.5.3.2.1 Input Selection
          2. 20.5.3.2.2 Reference Selection
          3. 20.5.3.2.3 LPM Bias and COMPA Enable
          4. 20.5.3.2.4 Resource Ownership and Usage
      4. 20.5.4 Comparator B (COMPB)
        1. 20.5.4.1 Introduction
        2. 20.5.4.2 Functional Description
          1. 20.5.4.2.1 Input Selection
          2. 20.5.4.2.2 Reference Selection
          3. 20.5.4.2.3 Resource Ownership and Usage
            1. 20.5.4.2.3.1 Sensor Controller Wakeup
            2. 20.5.4.2.3.2 System CPU Wakeup
      5. 20.5.5 Reference Digital-to-Analog Converter (DAC)
        1. 20.5.5.1 Introduction
        2. 20.5.5.2 Functional Description
          1. 20.5.5.2.1 Reference Selection
          2. 20.5.5.2.2 Output Voltage Control and Range
          3. 20.5.5.2.3 Sample Clock
            1. 20.5.5.2.3.1 Automatic Phase Control
            2. 20.5.5.2.3.2 Manual Phase Control
            3. 20.5.5.2.3.3 Operational Mode Dependency
          4. 20.5.5.2.4 Output Selection
            1. 20.5.5.2.4.1 Buffer
            2. 20.5.5.2.4.2 External Load
            3. 20.5.5.2.4.3 COMPA_REF
            4. 20.5.5.2.4.4 COMPB_REF
          5. 20.5.5.2.5 LPM Bias
          6. 20.5.5.2.6 Resource Ownership and Usage
      6. 20.5.6 Current Source (ISRC)
        1. 20.5.6.1 Introduction
        2. 20.5.6.2 Functional Description
          1. 20.5.6.2.1 Programmable Current
          2. 20.5.6.2.2 Voltage Reference
          3. 20.5.6.2.3 ISRC Enable
          4. 20.5.6.2.4 Temperature Dependency
          5. 20.5.6.2.5 Resource Ownership and Usage
    6. 20.6 Event Routing and Usage
      1. 20.6.1 AUX Event Bus
        1. 20.6.1.1 Event Signals
        2. 20.6.1.2 Event Subscribers
          1. 20.6.1.2.1 Event Detection
            1. 20.6.1.2.1.1 Detection of Asynchronous Events
            2. 20.6.1.2.1.2 Detection of Synchronous Events
      2. 20.6.2 Event Observation on External Pin
      3. 20.6.3 Events From MCU Domain
      4. 20.6.4 Events to MCU Domain
      5. 20.6.5 Events From AON Domain
      6. 20.6.6 Events to AON Domain
      7. 20.6.7 µDMA Interface
    7. 20.7 Sensor Controller Alias Register Space
    8. 20.8 AUX Domain Sensor Controller and Peripherals Registers
      1. 20.8.1  ADI_4_AUX Registers
      2. 20.8.2  AUX_AIODIO Registers
      3. 20.8.3  AUX_EVCTL Registers
      4. 20.8.4  AUX_SMPH Registers
      5. 20.8.5  AUX_TDC Registers
      6. 20.8.6  AUX_TIMER01 Registers
      7. 20.8.7  AUX_TIMER2 Registers
      8. 20.8.8  AUX_ANAIF Registers
      9. 20.8.9  AUX_SYSIF Registers
      10. 20.8.10 AUX_SPIM Registers
      11. 20.8.11 AUX_MAC Registers
      12. 20.8.12 AUX_SCE Registers
  22. 21Battery Monitor and Temperature Sensor (BATMON)
    1. 21.1 Introduction
    2. 21.2 Functional Description
    3. 21.3 AON_BATMON Registers
  23. 22Universal Asynchronous Receiver/Transmitter (UART)
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Signal Description
    4. 22.4 Functional Description
      1. 22.4.1 Transmit and Receive Logic
      2. 22.4.2 Baud Rate Generation
      3. 22.4.3 Data Transmission
      4. 22.4.4 Modem Handshake Support
        1. 22.4.4.1 Signaling
        2. 22.4.4.2 Flow Control
          1. 22.4.4.2.1 Hardware Flow Control (RTS and CTS)
          2. 22.4.4.2.2 Software Flow Control (Modem Status Interrupts)
      5. 22.4.5 FIFO Operation
      6. 22.4.6 Interrupts
      7. 22.4.7 Loopback Operation
    5. 22.5 Interface to µDMA
    6. 22.6 Initialization and Configuration
    7. 22.7 UART Registers
  24. 23Serial Peripheral Interface (SPI)
    1. 23.1 Introduction
    2. 23.2 Block Diagram
    3. 23.3 Signal Description
    4. 23.4 Functional Description
      1. 23.4.1 Bit Rate Generation
      2. 23.4.2 FIFO Operation
        1. 23.4.2.1 Transmit FIFO
          1. 23.4.2.1.1 Repeated Transmit Operation
        2. 23.4.2.2 Receive FIFO
        3. 23.4.2.3 FIFO Flush
      3. 23.4.3 Interrupts
      4. 23.4.4 Data Format
      5. 23.4.5 Delayed Data Sampling
      6. 23.4.6 Frame Formats
        1. 23.4.6.1 Texas Instruments Synchronous Serial Frame Format
        2. 23.4.6.2 Motorola SPI Frame Format
          1. 23.4.6.2.1 SPO Clock Polarity Bit
          2. 23.4.6.2.2 SPH Phase Control Bit
        3. 23.4.6.3 Motorola SPI Frame Format with SPO = 0 and SPH = 0
        4. 23.4.6.4 Motorola SPI Frame Format with SPO = 0 and SPH = 1
        5. 23.4.6.5 Motorola SPI Frame Format with SPO = 1 and SPH = 0
        6. 23.4.6.6 Motorola SPI Frame Format with SPO = 1 and SPH = 1
        7. 23.4.6.7 MICROWIRE Frame Format
    5. 23.5 μDMA Operation
    6. 23.6 Initialization and Configuration
    7. 23.7 SPI Registers
  25. 24Inter-Integrated Circuit (I2C)
    1. 24.1 Introduction
    2. 24.2 Block Diagram
    3. 24.3 Functional Description
      1. 24.3.1 I2C Bus Functional Overview
        1. 24.3.1.1 Start and Stop Conditions
        2. 24.3.1.2 Data Format with 7-Bit Address
        3. 24.3.1.3 Data Validity
        4. 24.3.1.4 Acknowledge
        5. 24.3.1.5 Arbitration
      2. 24.3.2 Available Speed Modes
        1. 24.3.2.1 Standard and Fast Modes
      3. 24.3.3 Interrupts
        1. 24.3.3.1 I2C Master Interrupts
        2. 24.3.3.2 I2C Slave Interrupts
      4. 24.3.4 Loopback Operation
      5. 24.3.5 Command Sequence Flow Charts
        1. 24.3.5.1 I2C Master Command Sequences
        2. 24.3.5.2 I2C Slave Command Sequences
    4. 24.4 Initialization and Configuration
    5. 24.5 I2C Registers
  26. 25Inter-IC Sound (I2S)
    1. 25.1 Introduction
    2. 25.2 Block Diagram
    3. 25.3 Signal Description
    4. 25.4 Functional Description
      1. 25.4.1 Dependencies
        1. 25.4.1.1 System CPU Deep-Sleep Mode
      2. 25.4.2 Pin Configuration
      3. 25.4.3 Serial Format Configuration
      4. 25.4.4 I2S
        1. 25.4.4.1 Register Configuration
      5. 25.4.5 Left-Justified (LJF)
        1. 25.4.5.1 Register Configuration
      6. 25.4.6 Right-Justified (RJF)
        1. 25.4.6.1 Register Configuration
      7. 25.4.7 DSP
        1. 25.4.7.1 Register Configuration
      8. 25.4.8 Clock Configuration
        1. 25.4.8.1 Internal Audio Clock Source
        2. 25.4.8.2 External Audio Clock Source
    5. 25.5 Memory Interface
      1. 25.5.1 Sample Word Length
      2. 25.5.2 Channel Mapping
      3. 25.5.3 Sample Storage in Memory
      4. 25.5.4 DMA Operation
        1. 25.5.4.1 Start-Up
        2. 25.5.4.2 Operation
        3. 25.5.4.3 Shutdown
    6. 25.6 Samplestamp Generator
      1. 25.6.1 Samplestamp Counters
      2. 25.6.2 Start-Up Triggers
      3. 25.6.3 Samplestamp Capture
      4. 25.6.4 Achieving Constant Audio Latency
    7. 25.7 Error Detection
    8. 25.8 Usage
      1. 25.8.1 Start-Up Sequence
      2. 25.8.2 Shutdown Sequence
    9. 25.9 I2S Registers
  27. 26Radio
    1. 26.1  RF Core
      1. 26.1.1 High-Level Description and Overview
    2. 26.2  Radio Doorbell
      1. 26.2.1 Special Boot Process
      2. 26.2.2 Command and Status Register and Events
      3. 26.2.3 RF Core Interrupts
        1. 26.2.3.1 RF Command and Packet Engine Interrupts
        2. 26.2.3.2 RF Core Hardware Interrupts
        3. 26.2.3.3 RF Core Command Acknowledge Interrupt
      4. 26.2.4 Radio Timer
        1. 26.2.4.1 Compare and Capture Events
        2. 26.2.4.2 Radio Timer Outputs
        3. 26.2.4.3 Synchronization with Real-Time Clock
    3. 26.3  RF Core HAL
      1. 26.3.1 Hardware Support
      2. 26.3.2 Firmware Support
        1. 26.3.2.1 Commands
        2. 26.3.2.2 Command Status
        3. 26.3.2.3 Interrupts
        4. 26.3.2.4 Passing Data
        5. 26.3.2.5 Command Scheduling
          1. 26.3.2.5.1 Triggers
          2. 26.3.2.5.2 Conditional Execution
          3. 26.3.2.5.3 Handling Before Start of Command
        6. 26.3.2.6 Command Data Structures
          1. 26.3.2.6.1 Radio Operation Command Structure
        7. 26.3.2.7 Data Entry Structures
          1. 26.3.2.7.1 Data Entry Queue
          2. 26.3.2.7.2 Data Entry
          3. 26.3.2.7.3 Pointer Entry
          4. 26.3.2.7.4 Partial Read RX Entry
        8. 26.3.2.8 External Signaling
      3. 26.3.3 Command Definitions
        1. 26.3.3.1 Protocol-Independent Radio Operation Commands
          1. 26.3.3.1.1  CMD_NOP: No Operation Command
          2. 26.3.3.1.2  CMD_RADIO_SETUP: Set Up Radio Settings Command
          3. 26.3.3.1.3  CMD_FS_POWERUP: Power Up Frequency Synthesizer
          4. 26.3.3.1.4  CMD_FS_POWERDOWN: Power Down Frequency Synthesizer
          5. 26.3.3.1.5  CMD_FS: Frequency Synthesizer Controls Command
          6. 26.3.3.1.6  CMD_FS_OFF: Turn Off Frequency Synthesizer
          7. 26.3.3.1.7  CMD_RX_TEST: Receiver Test Command
          8. 26.3.3.1.8  CMD_TX_TEST: Transmitter Test Command
          9. 26.3.3.1.9  CMD_SYNC_STOP_RAT: Synchronize and Stop Radio Timer Command
          10. 26.3.3.1.10 CMD_SYNC_START_RAT: Synchronously Start Radio Timer Command
          11. 26.3.3.1.11 CMD_COUNT: Counter Command
          12. 26.3.3.1.12 CMD_SCH_IMM: Run Immediate Command as Radio Operation
          13. 26.3.3.1.13 CMD_COUNT_BRANCH: Counter Command with Branch of Command Chain
          14. 26.3.3.1.14 CMD_PATTERN_CHECK: Check a Value in Memory Against a Pattern
        2. 26.3.3.2 Protocol-Independent Direct and Immediate Commands
          1. 26.3.3.2.1  CMD_ABORT: ABORT Command
          2. 26.3.3.2.2  CMD_STOP: Stop Command
          3. 26.3.3.2.3  CMD_GET_RSSI: Read RSSI Command
          4. 26.3.3.2.4  CMD_UPDATE_RADIO_SETUP: Update Radio Settings Command
          5. 26.3.3.2.5  CMD_TRIGGER: Generate Command Trigger
          6. 26.3.3.2.6  CMD_GET_FW_INFO: Request Information on the Firmware Being Run
          7. 26.3.3.2.7  CMD_START_RAT: Asynchronously Start Radio Timer Command
          8. 26.3.3.2.8  CMD_PING: Respond with Interrupt
          9. 26.3.3.2.9  CMD_READ_RFREG: Read RF Core Register
          10. 26.3.3.2.10 CMD_SET_RAT_CMP: Set RAT Channel to Compare Mode
          11. 26.3.3.2.11 CMD_SET_RAT_CPT: Set RAT Channel to Capture Mode
          12. 26.3.3.2.12 CMD_DISABLE_RAT_CH: Disable RAT Channel
          13. 26.3.3.2.13 CMD_SET_RAT_OUTPUT: Set RAT Output to a Specified Mode
          14. 26.3.3.2.14 CMD_ARM_RAT_CH: Arm RAT Channel
          15. 26.3.3.2.15 CMD_DISARM_RAT_CH: Disarm RAT Channel
          16. 26.3.3.2.16 CMD_SET_TX_POWER: Set Transmit Power
          17. 26.3.3.2.17 CMD_SET_TX20_POWER: Set Transmit Power of the 20 dBm PA
          18. 26.3.3.2.18 CMD_MODIFY_FS: Set New Synthesizer Frequency Without Recalibration
          19. 26.3.3.2.19 CMD_BUS_REQUEST: Request System BUS Available for RF Core
      4. 26.3.4 Immediate Commands for Data Queue Manipulation
        1. 26.3.4.1 CMD_ADD_DATA_ENTRY: Add Data Entry to Queue
        2. 26.3.4.2 CMD_REMOVE_DATA_ENTRY: Remove First Data Entry from Queue
        3. 26.3.4.3 CMD_FLUSH_QUEUE: Flush Queue
        4. 26.3.4.4 CMD_CLEAR_RX: Clear All RX Queue Entries
        5. 26.3.4.5 CMD_REMOVE_PENDING_ENTRIES: Remove Pending Entries from Queue
    4. 26.4  Data Queue Usage
      1. 26.4.1 Operations on Data Queues Available Only for Internal Radio CPU Operations
        1. 26.4.1.1 PROC_ALLOCATE_TX: Allocate TX Entry for Reading
        2. 26.4.1.2 PROC_FREE_DATA_ENTRY: Free Allocated Data Entry
        3. 26.4.1.3 PROC_FINISH_DATA_ENTRY: Finish Use of First Data Entry From Queue
        4. 26.4.1.4 PROC_ALLOCATE_RX: Allocate RX Buffer for Storing Data
        5. 26.4.1.5 PROC_FINISH_RX: Commit Received Data to RX Data Entry
      2. 26.4.2 Radio CPU Usage Model
        1. 26.4.2.1 Receive Queues
        2. 26.4.2.2 Transmit Queues
    5. 26.5  IEEE 802.15.4
      1. 26.5.1 IEEE 802.15.4 Commands
        1. 26.5.1.1 IEEE 802.15.4 Radio Operation Command Structures
        2. 26.5.1.2 IEEE 802.15.4 Immediate Command Structures
        3. 26.5.1.3 Output Structures
        4. 26.5.1.4 Other Structures and Bit Fields
      2. 26.5.2 Interrupts
      3. 26.5.3 Data Handling
        1. 26.5.3.1 Receive Buffers
        2. 26.5.3.2 Transmit Buffers
      4. 26.5.4 Radio Operation Commands
        1. 26.5.4.1 RX Operation
          1. 26.5.4.1.1 Frame Filtering and Source Matching
            1. 26.5.4.1.1.1 Frame Filtering
            2. 26.5.4.1.1.2 Source Matching
          2. 26.5.4.1.2 Frame Reception
          3. 26.5.4.1.3 ACK Transmission
          4. 26.5.4.1.4 End of Receive Operation
          5. 26.5.4.1.5 CCA Monitoring
        2. 26.5.4.2 Energy Detect Scan Operation
        3. 26.5.4.3 CSMA-CA Operation
        4. 26.5.4.4 Transmit Operation
        5. 26.5.4.5 Receive Acknowledgment Operation
        6. 26.5.4.6 Abort Background-Level Operation Command
      5. 26.5.5 Immediate Commands
        1. 26.5.5.1 Modify CCA Parameter Command
        2. 26.5.5.2 Modify Frame-Filtering Parameter Command
        3. 26.5.5.3 Enable or Disable Source Matching Entry Command
        4. 26.5.5.4 Abort Foreground-Level Operation Command
        5. 26.5.5.5 Stop Foreground-Level Operation Command
        6. 26.5.5.6 Request CCA and RSSI Information Command
    6. 26.6  Bluetooth® Low Energy
      1. 26.6.1 Bluetooth® Low Energy Commands
        1. 26.6.1.1 Command Data Definitions
          1. 26.6.1.1.1 Bluetooth® Low Energy Command Structures
        2. 26.6.1.2 Parameter Structures
        3. 26.6.1.3 Output Structures
        4. 26.6.1.4 Other Structures and Bit Fields
      2. 26.6.2 Interrupts
    7. 26.7  Data Handling
      1. 26.7.1 Receive Buffers
      2. 26.7.2 Transmit Buffers
    8. 26.8  Radio Operation Command Descriptions
      1. 26.8.1  Bluetooth® 5 Radio Setup Command
      2. 26.8.2  Radio Operation Commands for Bluetooth® Low Energy Packet Transfer
      3. 26.8.3  Coding Selection for Coded PHY
      4. 26.8.4  Parameter Override
      5. 26.8.5  Link Layer Connection
      6. 26.8.6  Slave Command
      7. 26.8.7  Master Command
      8. 26.8.8  Legacy Advertiser
        1. 26.8.8.1 Connectable Undirected Advertiser Command
        2. 26.8.8.2 Connectable Directed Advertiser Command
        3. 26.8.8.3 Non-connectable Advertiser Command
        4. 26.8.8.4 Scannable Undirected Advertiser Command
      9. 26.8.9  Bluetooth® 5 Advertiser Commands
        1. 26.8.9.1 Common Extended Advertising Packets
        2. 26.8.9.2 Extended Advertiser Command
        3. 26.8.9.3 Secondary Channel Advertiser Command
      10. 26.8.10 Scanner Commands
        1. 26.8.10.1 Scanner Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.10.2 Scanner Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.10.3 Scanner Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.10.4 ADI Filtering
        5. 26.8.10.5 End of Scanner Commands
      11. 26.8.11 Initiator Command
        1. 26.8.11.1 Initiator Receiving Legacy Advertising Packets on Primary Channel
        2. 26.8.11.2 Initiator Receiving Extended Advertising Packets on Primary Channel
        3. 26.8.11.3 Initiator Receiving Extended Advertising Packets on Secondary Channel
        4. 26.8.11.4 Automatic Window Offset Insertion
        5. 26.8.11.5 End of Initiator Commands
      12. 26.8.12 Generic Receiver Command
      13. 26.8.13 PHY Test Transmit Command
      14. 26.8.14 Whitelist Processing
      15. 26.8.15 Backoff Procedure
      16. 26.8.16 AUX Pointer Processing
      17. 26.8.17 Dynamic Change of Device Address
    9. 26.9  Immediate Commands
      1. 26.9.1 Update Advertising Payload Command
    10. 26.10 Proprietary Radio
      1. 26.10.1 Packet Formats
      2. 26.10.2 Commands
        1. 26.10.2.1 Command Data Definitions
          1. 26.10.2.1.1 Command Structures
        2. 26.10.2.2 Output Structures
        3. 26.10.2.3 Other Structures and Bit Fields
      3. 26.10.3 Interrupts
      4. 26.10.4 Data Handling
        1. 26.10.4.1 Receive Buffers
        2. 26.10.4.2 Transmit Buffers
      5. 26.10.5 Radio Operation Command Descriptions
        1. 26.10.5.1 End of Operation
        2. 26.10.5.2 Proprietary Mode Setup Command
          1. 26.10.5.2.1 IEEE 802.15.4g Packet Format
        3. 26.10.5.3 Transmitter Commands
          1. 26.10.5.3.1 Standard Transmit Command, CMD_PROP_TX
          2. 26.10.5.3.2 Advanced Transmit Command, CMD_PROP_TX_ADV
        4. 26.10.5.4 Receiver Commands
          1. 26.10.5.4.1 Standard Receive Command, CMD_PROP_RX
          2. 26.10.5.4.2 Advanced Receive Command, CMD_PROP_RX_ADV
        5. 26.10.5.5 Carrier-Sense Operation
          1. 26.10.5.5.1 Common Carrier-Sense Description
          2. 26.10.5.5.2 Carrier-Sense Command, CMD_PROP_CS
          3. 26.10.5.5.3 Sniff Mode Receiver Commands, CMD_PROP_RX_SNIFF and CMD_PROP_RX_ADV_SNIFF
      6. 26.10.6 Immediate Commands
        1. 26.10.6.1 Set Packet Length Command, CMD_PROP_SET_LEN
        2. 26.10.6.2 Restart Packet RX Command, CMD_PROP_RESTART_RX
    11. 26.11 Radio Registers
      1. 26.11.1 RFC_RAT Registers
      2. 26.11.2 RFC_DBELL Registers
      3. 26.11.3 RFC_PWR Registers
  28. 27Revision History

2.5.5 CPU_SCS Registers

Table 2-116 lists the memory-mapped registers for the CPU_SCS registers. All register offset addresses not listed in Table 2-116 should be considered as reserved locations and the register contents should not be modified.

Table 2-116 CPU_SCS Registers
OffsetAcronymRegister NameSection
0hCPUIDCPUID BaseSection 2.5.5.1
4hICSRInterrupt Control StateSection 2.5.5.2
8hVTORVector Table OffsetSection 2.5.5.3
ChAIRCRApplication Interrupt/Reset ControlSection 2.5.5.4
10hSCRSystem ControlSection 2.5.5.5
14hCCRConfiguration ControlSection 2.5.5.6
18hSHPR1System Handlers 4-7 PrioritySection 2.5.5.7
1ChSHPR2System Handlers 8-11 PrioritySection 2.5.5.8
20hSHPR3System Handlers 12-15 PrioritySection 2.5.5.9
24hSHCSRSystem Handler Control and StateSection 2.5.5.10
28hCFSRConfigurable Fault StatusSection 2.5.5.11
2ChHFSRHard Fault StatusSection 2.5.5.12
30hDFSRDebug Fault StatusSection 2.5.5.13
34hMMFARMem Manage Fault AddressSection 2.5.5.14
38hBFARBus Fault AddressSection 2.5.5.15
3ChAFSRAuxiliary Fault StatusSection 2.5.5.16
40hID_PFR0Processor Feature 0Section 2.5.5.17
44hID_PFR1Processor Feature 1Section 2.5.5.18
48hID_DFR0Debug Feature 0Section 2.5.5.19
4ChID_AFR0Auxiliary Feature 0Section 2.5.5.20
50hID_MMFR0Memory Model Feature 0Section 2.5.5.21
54hID_MMFR1Memory Model Feature 1Section 2.5.5.22
58hID_MMFR2Memory Model Feature 2Section 2.5.5.23
5ChID_MMFR3Memory Model Feature 3Section 2.5.5.24
60hID_ISAR0ISA Feature 0Section 2.5.5.25
64hID_ISAR1ISA Feature 1Section 2.5.5.26
68hID_ISAR2ISA Feature 2Section 2.5.5.27
6ChID_ISAR3ISA Feature 3Section 2.5.5.28
70hID_ISAR4ISA Feature 4Section 2.5.5.29

Complex bit access types are encoded to fit into small table cells. Table 2-117 shows the codes that are used for access types in this section.

Table 2-117 CPU_SCS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

2.5.5.1 CPUID Register (Offset = 0h) [Reset = 410FD214h]

CPUID is shown in Table 2-118.

Return to the Summary Table.

CPUID Base
This register determines the ID number of the processor core, the version number of the processor core and the implementation details of the processor core.

Table 2-118 CPUID Register Field Descriptions
BitFieldTypeResetDescription
31-24IMPLEMENTERR41hImplementor code.
23-20VARIANTR0hImplementation defined variant number.
19-16CONSTANTRFhReads as 0xF
15-4PARTNORD21hNumber of processor within family.
3-0REVISIONR4hImplementation defined revision number.

2.5.5.2 ICSR Register (Offset = 4h) [Reset = 00000000h]

ICSR is shown in Table 2-119.

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Interrupt Control State
This register is used to set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, and check the vector number of the active exception.

Table 2-119 ICSR Register Field Descriptions
BitFieldTypeResetDescription
31NMIPENDSETR/W0hSet pending NMI bit. Setting this bit pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.
0: No action
1: Set pending NMI
30PENDNMICLRR/W0hPend NMI clear. Allows the NMI exception pending state to be cleared.
0x0 No effect.
0x1 Clear pending status.
29RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
28PENDSVSETR/W0hSet pending pendSV bit.
0: No action
1: Set pending PendSV
27PENDSVCLRWXClear pending pendSV bit
0: No action
1: Clear pending pendSV
26PENDSTSETR/W0hSet a pending SysTick bit.
0: No action
1: Set pending SysTick
25PENDSTCLRWXClear pending SysTick bit
0: No action
1: Clear pending SysTick
24STTNSR0hSysTick Targets Non-secure. Controls whether in a single SysTick implementation, the SysTick is Secure or
Non-secure.
0x0 SysTick is Secure.
0x1 SysTick is Non-secure.
23ISRPREEMPTR0hThis field can only be used at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, the interrupt is serviced.
0: A pending exception is not serviced.
1: A pending exception is serviced on exit from the debug halt state
22ISRPENDINGR0hInterrupt pending flag. Excludes NMI and faults.
0x0: Interrupt not pending
0x1: Interrupt pending
21RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
20-12VECTPENDINGR0hPending ISR number field. This field contains the interrupt number of the highest priority pending ISR.
11RETTOBASER0hIndicates whether there are preempted active exceptions:
0: There are preempted active exceptions to execute
1: There are no active exceptions, or the currently-executing exception is the only active exception.
10-9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8-0VECTACTIVER0hActive ISR number field. Reset clears this field.

2.5.5.3 VTOR Register (Offset = 8h) [Reset = 00000000h]

VTOR is shown in Table 2-120.

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Vector Table Offset
This register is used to relocated the vector table base address. The vector table base offset determines the offset from the bottom of the memory map. The two most significant bits and the seven least significant bits of the vector table base offset must be 0. The portion of vector table base offset that is allowed to change is TBLOFF.

Table 2-120 VTOR Register Field Descriptions
BitFieldTypeResetDescription
31-7TBLOFFR/W0hBits 31 down to 7 of the vector table base offset.
6-0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.4 AIRCR Register (Offset = Ch) [Reset = FA050000h]

AIRCR is shown in Table 2-121.

Return to the Summary Table.

Application Interrupt/Reset Control
This register is used to determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point).

Table 2-121 AIRCR Register Field Descriptions
BitFieldTypeResetDescription
31-16VECTKEYR/WFA05hRegister key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. Otherwise the write value is ignored. Read always returns 0xFA05.
15ENDIANESSR0hData endianness bit
0h = Little endian
1h = Big endian
14PRISR0hPrioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is
enabled.
13BFHFNMINSR/W0hBusFault, HardFault, and NMI Non-secure enable. The value of this bit defines whether BusFault and NMI
exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception
0x0 BusFault, HardFault, and NMI are Secure.
0x1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
12-11RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
10-8PRIGROUPR/W0hInterrupt priority grouping field. This field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.
7-4RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
3SYSRESETREQSR/W0hSystem reset request Secure only. The value of this bit defines whether the SYSRESETREQ bit is functional
for Non-secure use
2SYSRESETREQW0hRequests a warm reset. Setting this bit does not prevent Halting Debug from running.
1VECTCLRACTIVEW0hClears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. This bit is for returning to a known state during debug. The bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.
0RESERVEDW0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.5 SCR Register (Offset = 10h) [Reset = 00000000h]

SCR is shown in Table 2-122.

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System Control
This register is used for power-management functions, i.e., signaling to the system when the processor can enter a low power state, controlling how the processor enters and exits low power states.

Table 2-122 SCR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4SEVONPENDR/W0hSend Event on Pending bit:
0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If
the processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction.
3SLEEPDEEPSR/W0hSleep deep secure. This field controls whether the SLEEPDEEP bit is only accessible from the Secure state
2SLEEPDEEPR/W0hControls whether the processor uses sleep or deep sleep as its low power mode
0h = Sleep
1h = Deep sleep
1SLEEPONEXITR/W0hSleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.
0: Do not sleep when returning to thread mode
1: Sleep on ISR exit
0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.6 CCR Register (Offset = 14h) [Reset = 00000001h]

CCR is shown in Table 2-123.

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Configuration Control
This register is used to enable NMI, HardFault and FAULTMASK to ignore bus fault, trap divide by zero and unaligned accesses, enable user access to the Software Trigger Interrupt Register (STIR), control entry to Thread Mode.

Table 2-123 CCR Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8BFHFNMIGNR/W0hEnables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. This applies to the HardFault, NMI, and FAULTMASK escalated handlers:
0: Data BusFaults caused by load and store instructions cause a lock-up
1: Data BusFaults caused by load and store instructions are ignored.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use
of this bit is to probe system devices and bridges to detect problems.
7-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4DIV_0_TRPR/W0hEnables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0: Do not trap divide by 0. In this mode, a divide by zero returns a quotient of 0.
1: Trap divide by 0. The relevant Usage Fault Status Register bit is CFSR.DIVBYZERO.
3UNALIGN_TRPR/W0hEnables unaligned access traps:
0: Do not trap unaligned halfword and word accesses
1: Trap unaligned halfword and word accesses. The relevant Usage Fault Status Register bit is CFSR.UNALIGNED.
If this bit is set to 1, an unaligned access generates a UsageFault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of the value in UNALIGN_TRP.
2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1USERSETMPENDR/W0hEnables unprivileged software access to STIR:
0: User code is not allowed to write to the Software Trigger Interrupt register (STIR).
1: User code can write the Software Trigger Interrupt register (STIR) to trigger (pend) a Main exception, which is associated with the Main stack pointer.
0RESERVEDR1hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.7 SHPR1 Register (Offset = 18h) [Reset = 00000000h]

SHPR1 is shown in Table 2-124.

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System Handlers 4-7 Priority
This register is used to prioritize the following system handlers: Memory manage, Bus fault, and Usage fault. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Table 2-124 SHPR1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16PRI_6R/W0hPriority of system handler 6. UsageFault
15-8PRI_5R/W0hPriority of system handler 5: BusFault
7-0PRI_4R/W0hPriority of system handler 4: MemManage

2.5.5.8 SHPR2 Register (Offset = 1Ch) [Reset = 00000000h]

SHPR2 is shown in Table 2-125.

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System Handlers 8-11 Priority
This register is used to prioritize the SVC handler. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Table 2-125 SHPR2 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_11R/W0hPriority of system handler 11. SVCall
23-0RESERVEDR0hReserved

2.5.5.9 SHPR3 Register (Offset = 20h) [Reset = 00000000h]

SHPR3 is shown in Table 2-126.

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System Handlers 12-15 Priority
This register is used to prioritize the following system handlers: SysTick, PendSV and Debug Monitor. System Handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

Table 2-126 SHPR3 Register Field Descriptions
BitFieldTypeResetDescription
31-24PRI_15R/W0hPriority of system handler 15. SysTick exception
23-16PRI_14R/W0hPriority of system handler 14. Pend SV
15-8RESERVEDR0hReserved
7-0PRI_12R/W0hPriority of system handler 12. Debug Monitor

2.5.5.10 SHCSR Register (Offset = 24h) [Reset = 00000000h]

SHCSR is shown in Table 2-127.

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System Handler Control and State
This register is used to enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.

Table 2-127 SHCSR Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
21HARDFAULTPENDEDR0hSecureFault exception pended state
0h = Exception is not active
1h = Exception is pending.
20SECUREFAULTPENDEDR0hSecureFault exception pended state
0h = Exception is not active
1h = Exception is pending.
19SECUREFAULTENAR/W0hSecureFault exception enable.
0h = Exception disabled
1h = Exception enabled
18USGFAULTENAR/W0hUsage fault system handler enable
0h = Exception disabled
1h = Exception enabled
17BUSFAULTENAR/W0hBus fault system handler enable
0h = Exception disabled
1h = Exception enabled
16MEMFAULTENAR/W0hMemManage fault system handler enable
0h = Exception disabled
1h = Exception enabled
15SVCALLPENDEDR0hSVCall pending
0h = Exception is not active
1h = Exception is pending.
14BUSFAULTPENDEDR0hBusFault pending
0h = Exception is not active
1h = Exception is pending.
13MEMFAULTPENDEDR0hMemManage exception pending
0h = Exception is not active
1h = Exception is pending.
12USGFAULTPENDEDR0hUsage fault pending
0h = Exception is not active
1h = Exception is pending.
11SYSTICKACTR0hSysTick active flag.
0x0: Not active
0x1: Active
0h = Exception is not active
1h = Exception is active
10PENDSVACTR0hPendSV active
0x0: Not active
0x1: Active
9RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
8MONITORACTR0hDebug monitor active
0h = Exception is not active
1h = Exception is active
7SVCALLACTR0hSVCall active
0h = Exception is not active
1h = Exception is active
6RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
5NMIACTR0hNMI exception active state
0h = Exception is not active
1h = Exception is active
4SECUREFAULTACTR0hSecureFault exception active state
0h = Exception is not active
1h = Exception is active
3USGFAULTACTR0hUsageFault exception active
0h = Exception is not active
1h = Exception is active
2HARDFAULTACTR0hHardFault exception active state. Indicates and allows limited modification of the active state of the HardFault exception for the selected Security state
0h = Exception is not active
1h = Exception is active
1BUSFAULTACTR0hBusFault exception active
0h = Exception is not active
1h = Exception is active
0MEMFAULTACTR0hMemManage exception active
0h = Exception is not active
1h = Exception is active

2.5.5.11 CFSR Register (Offset = 28h) [Reset = 00000000h]

CFSR is shown in Table 2-128.

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Configurable Fault Status
This register is used to obtain information about local faults. These registers include three subsections: The first byte is Memory Manage Fault Status Register (MMFSR). The second byte is Bus Fault Status Register (BFSR). The higher half-word is Usage Fault Status Register (UFSR). The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.
The CFSR is byte accessible. CFSR or its subregisters can be accessed as follows:
The following accesses are possible to the CFSR register:
- access the complete register with a word access to 0xE000ED28.
- access the MMFSR with a byte access to 0xE000ED28
- access the MMFSR and BFSR with a halfword access to 0xE000ED28
- access the BFSR with a byte access to 0xE000ED29
- access the UFSR with a halfword access to 0xE000ED2A.

Table 2-128 CFSR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
25DIVBYZEROR/W0hWhen CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0.
24UNALIGNEDR/W0hWhen CCR.UNALIGN_TRP is enabled, and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of CCR.UNALIGN_TRP.
23-20RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
19NOCPR/W0hAttempt to use a coprocessor instruction. The processor does not support coprocessor instructions.
18INVPCR/W0hAttempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.
17INVSTATER/W0hIndicates an attempt to execute in an invalid EPSR state (e.g. after a BX type instruction has changed state). This includes state change after entry to or return from exception, as well as from inter-working instructions. Return PC points to faulting instruction, with the invalid state.
16UNDEFINSTRR/W0hThis bit is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.
15BFARVALIDR/W0hThis bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.
14-13RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
12STKERRR/W0hStacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. BFAR is not written.
11UNSTKERRR/W0hUnstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. BFAR is not written.
10IMPRECISERRR/W0hImprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. BFAR is not written.
9PRECISERRR/W0hPrecise data bus error return.
8IBUSERRR/W0hInstruction bus error flag. This flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. BFAR is not written.
7MMARVALIDR/W0hMemory Manage Address Register (MMFAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMFAR value has been overwritten.
6-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4MSTKERRR/W0hStacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. MMFAR is not written.
3MUNSTKERRR/W0hUnstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. MMFAR is not written.
2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1DACCVIOLR/W0hData access violation flag. Attempting to load or store at a location that does not permit the operation sets this flag. The return PC points to the faulting instruction. This error loads MMFAR with the address of the attempted access.
0IACCVIOLR/W0hInstruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets this flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. MMFAR is not written.

2.5.5.12 HFSR Register (Offset = 2Ch) [Reset = 00000000h]

HFSR is shown in Table 2-129.

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Hard Fault Status
This register is used to obtain information about events that activate the Hard Fault handler. This register is a write-clear register. This means that writing a 1 to a bit clears that bit.

Table 2-129 HFSR Register Field Descriptions
BitFieldTypeResetDescription
31DEBUGEVTR/W1C0hThis bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.
30FORCEDR/W1C0hHard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.
29-2RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
1VECTTBLR/W1C0hThis bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.
0RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.13 DFSR Register (Offset = 30h) [Reset = 00000000h]

DFSR is shown in Table 2-130.

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Debug Fault Status
This register is used to monitor external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit. Note that these bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and some are ignored.

Table 2-130 DFSR Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/W0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
4EXTERNALR/W0hExternal debug request flag. The processor stops on next instruction boundary.
0x0: External debug request signal not asserted
0x1: External debug request signal asserted
3VCATCHR/W0hVector catch flag. When this flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.
0x0: No vector catch occurred
0x1: Vector catch occurred
2DWTTRAPR/W0hData Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction.
0x0: No DWT match
0x1: DWT match
1BKPTR/W0hBKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.
0x0: No BKPT instruction execution
0x1: BKPT instruction execution
0HALTEDR/W0hHalt request flag. The processor is halted on the next instruction.
0x0: No halt request
0x1: Halt requested by NVIC, including step

2.5.5.14 MMFAR Register (Offset = 34h) [Reset = 00000000h]

MMFAR is shown in Table 2-131.

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Mem Manage Fault Address
This register is used to read the address of the location that caused a Memory Manage Fault.

Table 2-131 MMFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WXMem Manage fault address field.
This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination with CFSR.MMARVALIDindicate the cause of the fault.

2.5.5.15 BFAR Register (Offset = 38h) [Reset = 00000000h]

BFAR is shown in Table 2-132.

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Bus Fault Address
This register is used to read the address of the location that generated a Bus Fault.

Table 2-132 BFAR Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WXBus fault address field. This field is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted.
Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the fault.

2.5.5.16 AFSR Register (Offset = 3Ch) [Reset = 00000000h]

AFSR is shown in Table 2-133.

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Auxiliary Fault Status
This register is used to determine additional system fault information to software. Single-cycle high level on an auxiliary faults is latched as one. The bit can only be cleared by writing a one to the corresponding bit. Auxiliary fault inputs to the CPU are tied to 0.

Table 2-133 AFSR Register Field Descriptions
BitFieldTypeResetDescription
31-0IMPDEFR/W0hImplementation defined. The bits map directly onto the signal assignment to the auxiliary fault inputs. Tied to 0

2.5.5.17 ID_PFR0 Register (Offset = 40h) [Reset = 00000030h]

ID_PFR0 is shown in Table 2-134.

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Processor Feature 0

Table 2-134 ID_PFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
7-4STATE1R3hState1 (T-bit == 1)
0x0: N/A
0x1: N/A
0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.)
0x3: Thumb-2 encoding with all Thumb-2 basic instructions
3-0STATE0R0hState0 (T-bit == 0)
0x0: No ARM encoding
0x1: N/A

2.5.5.18 ID_PFR1 Register (Offset = 44h) [Reset = 00000210h]

ID_PFR1 is shown in Table 2-135.

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Processor Feature 1

Table 2-135 ID_PFR1 Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
11-8

MICROCONTROLLER_

PROGRAMMERS_MODEL

 R 2h Microcontroller programmer's model
0x0: Not supported
0x2: Two-stack support
7-4 SECURITY R 1h Security. Identifies whether the Security Extension is implemented
3-0 RESERVED R 0h Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.19 ID_DFR0 Register (Offset = 48h) [Reset = 00100000h]

ID_DFR0 is shown in Table 2-136.

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Debug Feature 0
This register provides a high level view of the debug system. Further details are provided in the debug infrastructure itself.

Table 2-136 ID_DFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
23-20

MICROCONTROLLER_

DEBUG_MODEL

R1hMicrocontroller Debug Model - memory mapped
0x0: Not supported
0x1: Microcontroller debug v1 (ITMv1 and DWTv1)
19-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.20 ID_AFR0 Register (Offset = 4Ch) [Reset = 00000000h]

ID_AFR0 is shown in Table 2-137.

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Auxiliary Feature 0
This register provides some freedom for implementation defined features to be registered. Not used in Cortex-M.

Table 2-137 ID_AFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.21 ID_MMFR0 Register (Offset = 50h) [Reset = 00100030h]

ID_MMFR0 is shown in Table 2-138.

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Memory Model Feature 0
General information on the memory model and memory management support.

Table 2-138 ID_MMFR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR00100030hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.22 ID_MMFR1 Register (Offset = 54h) [Reset = 00000000h]

ID_MMFR1 is shown in Table 2-139.

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Memory Model Feature 1
General information on the memory model and memory management support.

Table 2-139 ID_MMFR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.23 ID_MMFR2 Register (Offset = 58h) [Reset = 01000000h]

ID_MMFR2 is shown in Table 2-140.

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Memory Model Feature 2
General information on the memory model and memory management support.

Table 2-140 ID_MMFR2 Register Field Descriptions
Bit Field Type Reset Description
31-28 RESERVED R 0h Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
27-24

WAIT_FOR_INTERRUPT_

STALLING

 R 1h wait for interrupt stalling
0x0: Not supported
0x1: Wait for interrupt supported
23-0 RESERVED R 0h Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.24 ID_MMFR3 Register (Offset = 5Ch) [Reset = 00000000h]

ID_MMFR3 is shown in Table 2-141.

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Memory Model Feature 3
General information on the memory model and memory management support.

Table 2-141 ID_MMFR3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.25 ID_ISAR0 Register (Offset = 60h) [Reset = 01101110h]

ID_ISAR0 is shown in Table 2-142.

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ISA Feature 0
Information on the instruction set attributes register

Table 2-142 ID_ISAR0 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01101110hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.26 ID_ISAR1 Register (Offset = 64h) [Reset = 02112000h]

ID_ISAR1 is shown in Table 2-143.

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ISA Feature 1
Information on the instruction set attributes register

Table 2-143 ID_ISAR1 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR02112000hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.27 ID_ISAR2 Register (Offset = 68h) [Reset = 21232231h]

ID_ISAR2 is shown in Table 2-144.

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ISA Feature 2
Information on the instruction set attributes register

Table 2-144 ID_ISAR2 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR21232231hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.28 ID_ISAR3 Register (Offset = 6Ch) [Reset = 01111131h]

ID_ISAR3 is shown in Table 2-145.

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ISA Feature 3
Information on the instruction set attributes register

Table 2-145 ID_ISAR3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01111131hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

2.5.5.29 ID_ISAR4 Register (Offset = 70h) [Reset = 01310132h]

ID_ISAR4 is shown in Table 2-146.

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ISA Feature 4
Information on the instruction set attributes register

Table 2-146 ID_ISAR4 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR01310132hSoftware should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.