SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 23-2 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 23-2 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
20h | IIDX | This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, and 31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. | Section 23.7.1 |
28h | IMASK | Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS. | Section 23.7.2 |
30h | RIS | Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. | Section 23.7.3 |
38h | MIS | Masked interrupt status. This is an AND of the IMASK and RIS registers. | Section 23.7.4 |
40h | ISET | Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set. | Section 23.7.5 |
48h | ICLR | Interrupt clear. Write a 1 to clear the corresponding Interrupt. | Section 23.7.6 |
E0h | EVT_MODE | Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS) | Section 23.7.7 |
FCh | DESC | This register identifies the peripheral and its exact version. | Section 23.7.8 |
100h | CTL0 | SPI Control Register 0 | Section 23.7.9 |
104h | CTL1 | SPI Control Register 1 | Section 23.7.10 |
108h | CLKCTL | Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings. | Section 23.7.11 |
10Ch | IFLS | The IFLS register is the interrupt FIFO level select register. This register can be used to define the levels at which the TX, RX FIFO interrupt flags are triggered. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. | Section 23.7.12 |
110h | STAT | Status Register | Section 23.7.13 |
114h | CLKDIV2 | This register is used to specify a divide ratio of the SPI functional clock. | Section 23.7.14 |
118h | DMACR | DMA Control Register | Section 23.7.15 |
130h | RXDATA | RXDATA Register. Reading this register returns value in the RX FIFO pointed by the current FIFO read pointer. If the RX FIFO is empty, the last read value is returned. Writing has not effect and is ignored. | Section 23.7.16 |
140h | TXDATA | TXDATA Register. Writing into this register puts the data into the TX FIFO. Reading this register returns the last written value, pointed by the current FIFO write pointer. | Section 23.7.17 |
Complex bit access types are encoded to fit into small table cells. Table 23-3 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
IIDX is shown in Table 23-4.
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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, and 31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it would display 0x0.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-0 | STAT | R | 0h | Interrupt index status
0h = No interrupt pending 1h = RX FIFO Overflow Event/interrupt pending 2h = Transmit Parity Event/interrupt pending 3h = SPI Receive Time-Out Event/interrupt pending 4h = Receive Event/interrupt pending 5h = Transmit Event/interrupt pending 6h = Transmit Buffer Empty Event/interrupt pending 7h = End of Transmit Event/interrupt pending 8h = DMA Done for Receive Event/interrupt pending 9h = DMA Done for Transmit Event/interrupt pending |
IMASK is shown in Table 23-5.
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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | DMA_DONE_TX | R/W | 0h | DMA Done event for TX event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
7 | DMA_DONE_RX | R/W | 0h | DMA Done event for RX event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
6 | IDLE | R/W | 0h | SPI Idle event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
5 | TXEMPTY | R/W | 0h | Transmit FIFO Empty event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
4 | TX | R/W | 0h | Transmit FIFO event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
3 | RX | R/W | 0h | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
2 | RTOUT | R/W | 0h | SPI Receive Time-Out event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
1 | PER | R/W | 0h | Parity error event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
0 | RXFIFO_OVF | R/W | 0h | RXFIFO overflow event mask.
0h = Clear Interrupt Mask 1h = Set Interrupt Mask |
RIS is shown in Table 23-6.
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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | DMA_DONE_TX | R | 0h | DMA Done event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMA_DONE_RX | R | 0h | DMA Done event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
0h = Interrupt did not occur 1h = Interrupt occurred |
6 | IDLE | R | 0h | SPI has completed transfers and changed into IDLE mode. This bit is set when STAT.BUSY goes low.
0h = Interrupt did not occur 1h = Interrupt occurred |
5 | TXEMPTY | R | 0h | Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
0h = Interrupt did not occur 1h = Interrupt occurred |
4 | TX | R | 0h | Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur 1h = Interrupt occurred |
3 | RX | R | 0h | Receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | SPI Receive Time-Out event.
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | PER | R | 0h | Parity error event: this bit is set if a parity error has been detected
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RXFIFO_OVF | R | 0h | RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur 1h = Interrupt occurred |
MIS is shown in Table 23-7.
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Masked interrupt status. This is an AND of the IMASK and RIS registers.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | DMA_DONE_TX | R | 0h | Masked DMA Done event for TX.
0h = Interrupt did not occur 1h = Interrupt occurred |
7 | DMA_DONE_RX | R | 0h | Masked DMA Done event for RX.
0h = Interrupt did not occur 1h = Interrupt occurred |
6 | IDLE | R | 0h | Masked SPI IDLE mode event.
0h = Interrupt did not occur 1h = Interrupt occurred |
5 | TXEMPTY | R | 0h | Masked Transmit FIFO Empty event.
0h = Interrupt did not occur 1h = Interrupt occurred |
4 | TX | R | 0h | Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
0h = Interrupt did not occur 1h = Interrupt occurred |
3 | RX | R | 0h | Masked receive FIFO event. This interrupt is set if the selected Receive FIFO level has been reached
0h = Interrupt did not occur 1h = Interrupt occurred |
2 | RTOUT | R | 0h | Masked SPI Receive Time-Out Interrupt.
0h = Interrupt did not occur 1h = Interrupt occurred |
1 | PER | R | 0h | Masked Parity error event: this bit if a parity error has been detected
0h = Interrupt did not occur 1h = Interrupt occurred |
0 | RXFIFO_OVF | R | 0h | Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
0h = Interrupt did not occur 1h = Interrupt occurred |
ISET is shown in Table 23-8.
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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | DMA_DONE_TX | W | 0h | Set DMA Done event for TX.
0h = Writing 0 has no effect 1h = Set Interrupt |
7 | DMA_DONE_RX | W | 0h | Set DMA Done event for RX.
0h = Writing 0 has no effect 1h = Set Interrupt |
6 | IDLE | W | 0h | Set SPI IDLE mode event.
0h = Writing 0 has no effect 1h = Set Interrupt |
5 | TXEMPTY | W | 0h | Set Transmit FIFO Empty event.
0h = Writing 0 has no effect 1h = Set Interrupt |
4 | TX | W | 0h | Set Transmit FIFO event.
0h = Writing 0 has no effect 1h = Set Interrupt |
3 | RX | W | 0h | Set Receive FIFO event.
0h = Writing 0 has no effect 1h = Set Interrupt |
2 | RTOUT | W | 0h | Set SPI Receive Time-Out event.
0h = Writing 0 has no effect 1h = Set Interrupt |
1 | PER | W | 0h | Set Parity error event.
0h = Writing 0 has no effect 1h = Set Interrupt |
0 | RXFIFO_OVF | W | 0h | Set RXFIFO overflow event.
0h = Writing 0 has no effect 1h = Set Interrupt |
ICLR is shown in Table 23-9.
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Interrupt clear. Write a 1 to clear the corresponding Interrupt.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | DMA_DONE_TX | W | 0h | Clear DMA Done event for TX.
0h = Writing 0 has no effect 1h = Clear Interrupt |
7 | DMA_DONE_RX | W | 0h | Clear DMA Done event for RX.
0h = Writing 0 has no effect 1h = Clear Interrupt |
6 | IDLE | W | 0h | Clear SPI IDLE mode event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
5 | TXEMPTY | W | 0h | Clear Transmit FIFO Empty event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
4 | TX | W | 0h | Clear Transmit FIFO event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
3 | RX | W | 0h | Clear Receive FIFO event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
2 | RTOUT | W | 0h | Clear SPI Receive Time-Out event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
1 | PER | W | 0h | Clear Parity error event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
0 | RXFIFO_OVF | W | 0h | Clear RXFIFO overflow event.
0h = Writing 0 has no effect 1h = Clear Interrupt |
EVT_MODE is shown in Table 23-10.
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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)
Note: The recommendation is to use SPI in the software mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1-0 | INT0_CFG | R/W | 1h | Event line mode select for event corresponding to IPSTANDARD.INT_EVENT0
0h = The interrupt or event line is disabled. 1h = The interrupt or event line is in software mode. Software must clear the RIS. 2h = The interrupt or event line is in hardware mode. The hardware automatically clears the RIS flag. |
DESC is shown in Table 23-11.
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This register identifies the peripheral and its exact version.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODULEID | R | 1411h | Module identification contains a unique peripheral identification number. The assignments are maintained in a central database for all of the platform modules to ensure uniqueness. |
15-12 | FEATUREVER | R | 0h | Feature set version for this module instance. |
11-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | MAJREV | R | 1h | Major revision of the IP |
3-0 | MINREV | R | 0h | Minor revision of the IP |
CTL0 is shown in Table 23-12.
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SPI Control Register 0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-15 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
14 | CSCLR | R/W | 0h | Clear shift register counter when CS gets inactive. This bit is relevant only in the slave mode, CTL1.MS = 0.
0h = Disable automatic clear of shift register when CS gets inactive. 1h = Enable automatic clear of shift register when CS gets inactive. |
13-12 | RESERVED | R | 0h | Reserved |
11-10 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
9 | SPH | R/W | 0h | CLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge. 0h = Data is captured on the first clock edge transition. 1h = Data is captured on the second clock edge transition. |
8 | SPO | R/W | 0h | CLKOUT polarity (Motorola SPI frame format only)
0h = SPI produces a steady state LOW value on the CLKOUT when data is not being transferred. 1h = SPI produces a steady state HIGH value on the CLKOUT when data is not being transferred. |
7 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
6-5 | FRF | R/W | 0h | Frame format Select
0h = Motorola SPI frame format (3 wire mode) 1h = Motorola SPI frame format (4 wire mode) 2h = TI synchronous serial frame format 3h = National MICROWIRE frame format |
4-0 | DSS | R/W | 0h | Data Size Select. Note: Master mode: Values 0 - 2 are reserved and shall not be used. This will map to 4 bit mode. A value of 3h corresponds to 4-bit data (and so on). Slave mode: DSS should be no less than 6 which means the minimum frame length is 7 bits. 3h = Data Size Select bits: 4 4h = Data Size Select bits: 5 5h = Data Size Select bits: 6 6h = Data Size Select bits: 7 7h = Data Size Select bits: 8 8h = Data Size Select bits: 9 9h = Data Size Select bits: 10 Ah = Data Size Select bits: 11 Bh = Data Size Select bits: 12 Ch = Data Size Select bits: 13 Dh = Data Size Select bits: 14 Eh = Data Size Select bits: 15 Fh = Data Size Select bits: 16 10h = Data Size Select bits: 17 11h = Data Size Select bits: 18 12h = Data Size Select bits: 19 13h = Data Size Select bits: 20 14h = Data Size Select bits: 21 15h = Data Size Select bits: 22 16h = Data Size Select bits: 23 17h = Data Size Select bits: 24 18h = Data Size Select bits: 25 19h = Data Size Select bits: 26 1Ah = Data Size Select bits: 27 1Bh = Data Size Select bits: 28 1Ch = Data Size Select bits: 29 1Dh = Data Size Select bits: 30 1Eh = Data Size Select bits: 31 1Fh = Data Size Select bits: 32 |
CTL1 is shown in Table 23-13.
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SPI Control Register 1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
29-24 | RXTIMEOUT | R/W | 0h | Receive Timeout (only for Slave mode). This register defines the number of clock cycles after which the Receive Timeout interrupt is set. A value of 0 disables this function. 0h = Smallest value 3Fh = Highest possible value |
23-16 | REPEATTX | R/W | 0h | Counter to repeat last transfer. A value of 0 disables this feature. After a non-zero value (X) is written to this register, SPI transfer can be started with writing a data into the TX Buffer. The data will be transferred X+1 times in total. The behavior is identical as if the data were be written into the TX Buffer that many times as defined by the value here additionally. It can be used to clean a transfer or to pull a certain amount of data by a slave. This feature can be used only in the master mode. |
15-11 | RESERVED | R | 0h | Reserved |
10 | FIFORST | R/W | 0h | This bit is used to reset transmit and receive FIFO pointers. The pointers are held at a reset value until this bit is cleared to zero.
0h = Clear FIFO pointers reset trigger 1h = Set FIFO pointers reset trigger |
9-8 | RESERVED | R | 0h | Reserved |
7 | PBS | R/W | 0h | Parity Bit Select
0h = Bit 0 is used for Parity 1h = Bit 1 is used for Parity, Bit 0 is ignored |
6 | PES | R/W | 0h | Even Parity Select
0h = Odd Parity mode 1h = Even Parity mode |
5 | PEN | R/W | 0h | Parity enable if enabled the last bit will be used as parity to evaluate the right transmission of the previous bits. In case of a parity mismatch the parity error flag RIS.PER will be set. 0h = Disable Parity function 1h = Enable Parity function |
4 | MSB | R/W | 0h | MSB first select. Controls the direction of the receive and transmit shift register.
0h = LSB first 1h = MSB first |
3 | SOD | R/W | 0h | Slave-mode: Data output disabled This bit is relevant only in the slave mode, MS=0. In multiple-slave systems, it is possible for an SPI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RX lines from multiple slaves could be tied together. To operate in such systems, this bitfield can be set if the SPI slave is not supposed to drive the TX line. 0h = SPI can drive the MISO output via TX in slave mode. 1h = SPI cannot drive the MISO output via TX in slave mode. |
2 | MS | R/W | 1h | Master or slave mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE = 0.
0h = Select Slave Mode 1h = Select Master Mode |
1 | LBM | R/W | 0h | Loop back mode
0h = Disable loopback mode. Normal serial port operation enabled. 1h = Enable loopback mode.Output of transmit serial shifter is connected to input of receive serial shifter internally. |
0 | ENABLE | R/W | 0h | SPI enable
0h = Disable module function 1h = Enable module function |
CLKCTL is shown in Table 23-14.
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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | DSAMPLE | R/W | 0h | Delayed sampling. In master mode the data on the input pin will be sampled after the defined clock cycles. Note: As an example, if the SPI transmit frequency is set to 12 MHz in the master mode, DSAMPLE should be set to a value of 2 |
27-10 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
9-0 | SCR | R/W | 0h | Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023. 0h = Smallest value 3FFh = Highest possible value |
IFLS is shown in Table 23-15.
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The IFLS register is the interrupt FIFO level select register. This register can be used to define the levels at which the TX, RX FIFO interrupt flags are triggered. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
5-3 | RXIFLSEL | R/W | 2h | SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
0h = Reserved 1h = RX FIFO >= 1/4 full 2h = RX FIFO >= 1/2 full (default) 3h = RX FIFO >= 3/4 full 4h = Reserved 5h = RX FIFO is full 6h = Reserved 7h = Trigger when RX FIFO contains >= 1 byte |
2-0 | TXIFLSEL | R/W | 2h | SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
0h = Reserved 1h = TX FIFO <= 3/4 empty 2h = TX FIFO <= 1/2 empty (default) 3h = TX FIFO <= 1/4 empty 4h = Reserved 5h = TX FIFO is empty 6h = Reserved 7h = Trigger when TX FIFO has >= 1 byte free |
STAT is shown in Table 23-16.
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Status Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
4 | BUSY | R | 0h | Busy
0h = SPI is in idle mode. 1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty. |
3 | RNF | R | 1h | Receive FIFO not full
0h = Receive FIFO is full. 1h = Receive FIFO is not full. |
2 | RFE | R | 1h | Receive FIFO empty.
0h = Receive FIFO is not empty. 1h = Receive FIFO is empty. |
1 | TNF | R | 1h | Transmit FIFO not full
0h = Transmit FIFO is full. 1h = Transmit FIFO is not full. |
0 | TFE | R | 1h | Transmit FIFO empty.
0h = Transmit FIFO is not empty. 1h = Transmit FIFO is empty. |
CLKDIV2 is shown in Table 23-17.
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This register is used to specify a divide ratio of the SPI functional clock.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
2-0 | RATIO | R/W | 0h | Selects divide ratio of module clock
0h = Do not divide clock source 1h = Divide clock source by 2 2h = Divide clock source by 3 3h = Divide clock source by 4 4h = Divide clock source by 5 5h = Divide clock source by 6 6h = Divide clock source by 7 7h = Divide clock source by 8 |
DMACR is shown in Table 23-18.
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DMA Control Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1 | TXDMAE | R/W | 0h | Transmit FIFO DMA enable when set. |
0 | RXDMAE | R/W | 0h | Receive FIFO DMA enable when set. |
RXDATA is shown in Table 23-19.
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RXDATA Register. Reading this register returns value in the RX FIFO pointed by the current FIFO read pointer. If the RX FIFO is empty, the last read value is returned. Writing has not effect and is ignored.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R | 0h | Received Data |
TXDATA is shown in Table 23-20.
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TXDATA Register. Writing into this register puts the data into the TX FIFO. Reading this register returns the last written value, pointed by the current FIFO write pointer.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DATA | R/W | 0h | Transmit Data |