SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 15-40 lists the memory-mapped registers for the IOC registers. All register offset addresses not listed in Table 15-40 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | IOCFG0 | Configuration of DIO0 | Section 15.10.3.1 |
4h | IOCFG1 | Configuration of DIO1 | Section 15.10.3.2 |
8h | IOCFG2 | Configuration of DIO2 | Section 15.10.3.3 |
Ch | IOCFG3 | Configuration of DIO3 | Section 15.10.3.4 |
10h | IOCFG4 | Configuration of DIO4 | Section 15.10.3.5 |
14h | IOCFG5 | Configuration of DIO5 | Section 15.10.3.6 |
18h | IOCFG6 | Configuration of DIO6 | Section 15.10.3.7 |
1Ch | IOCFG7 | Configuration of DIO7 | Section 15.10.3.8 |
20h | IOCFG8 | Configuration of DIO8 | Section 15.10.3.9 |
24h | IOCFG9 | Configuration of DIO9 | Section 15.10.3.10 |
28h | IOCFG10 | Configuration of DIO10 | Section 15.10.3.11 |
2Ch | IOCFG11 | Configuration of DIO11 | Section 15.10.3.12 |
30h | IOCFG12 | Configuration of DIO12 | Section 15.10.3.13 |
34h | IOCFG13 | Configuration of DIO13 | Section 15.10.3.14 |
38h | IOCFG14 | Configuration of DIO14 | Section 15.10.3.15 |
3Ch | IOCFG15 | Configuration of DIO15 | Section 15.10.3.16 |
40h | IOCFG16 | Configuration of DIO16 | Section 15.10.3.17 |
44h | IOCFG17 | Configuration of DIO17 | Section 15.10.3.18 |
48h | IOCFG18 | Configuration of DIO18 | Section 15.10.3.19 |
4Ch | IOCFG19 | Configuration of DIO19 | Section 15.10.3.20 |
50h | IOCFG20 | Configuration of DIO20 | Section 15.10.3.21 |
54h | IOCFG21 | Configuration of DIO21 | Section 15.10.3.22 |
58h | IOCFG22 | Configuration of DIO22 | Section 15.10.3.23 |
5Ch | IOCFG23 | Configuration of DIO23 | Section 15.10.3.24 |
60h | IOCFG24 | Configuration of DIO24 | Section 15.10.3.25 |
64h | IOCFG25 | Configuration of DIO25 | Section 15.10.3.26 |
68h | IOCFG26 | Configuration of DIO26 | Section 15.10.3.27 |
6Ch | IOCFG27 | Configuration of DIO27 | Section 15.10.3.28 |
70h | IOCFG28 | Configuration of DIO28 | Section 15.10.3.29 |
74h | IOCFG29 | Configuration of DIO29 | Section 15.10.3.30 |
78h | IOCFG30 | Configuration of DIO30 | Section 15.10.3.31 |
7Ch | IOCFG31 | Configuration of DIO31 | Section 15.10.3.32 |
80h | IOCFG32 | Configuration of DIO32 | Section 15.10.3.33 |
84h | IOCFG33 | Configuration of DIO33 | Section 15.10.3.34 |
88h | IOCFG34 | Configuration of DIO34 | Section 15.10.3.35 |
8Ch | IOCFG35 | Configuration of DIO35 | Section 15.10.3.36 |
90h | IOCFG36 | Configuration of DIO36 | Section 15.10.3.37 |
94h | IOCFG37 | Configuration of DIO37 | Section 15.10.3.38 |
98h | IOCFG38 | Configuration of DIO38 | Section 15.10.3.39 |
9Ch | IOCFG39 | Configuration of DIO39 | Section 15.10.3.40 |
A0h | IOCFG40 | Configuration of DIO40 | Section 15.10.3.41 |
A4h | IOCFG41 | Configuration of DIO41 | Section 15.10.3.42 |
A8h | IOCFG42 | Configuration of DIO42 | Section 15.10.3.43 |
ACh | IOCFG43 | Configuration of DIO43 | Section 15.10.3.44 |
B0h | IOCFG44 | Configuration of DIO44 | Section 15.10.3.45 |
B4h | IOCFG45 | Configuration of DIO45 | Section 15.10.3.46 |
B8h | IOCFG46 | Configuration of DIO46 | Section 15.10.3.47 |
BCh | IOCFG47 | Configuration of DIO47 | Section 15.10.3.48 |
Complex bit access types are encoded to fit into small table cells. Table 15-41 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
IOCFG0 is shown in Table 15-42.
Return to the Summary Table.
Configuration of DIO0
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / outut 7h = OPENSRC_INV : Open Source Inverted input/output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO0 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG1 is shown in Table 15-43.
Return to the Summary Table.
Configuration of DIO1
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO1 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG2 is shown in Table 15-44.
Return to the Summary Table.
Configuration of DIO2
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO2 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG3 is shown in Table 15-45.
Return to the Summary Table.
Configuration of DIO3
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO3 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG4 is shown in Table 15-46.
Return to the Summary Table.
Configuration of DIO4
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO4 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG5 is shown in Table 15-47.
Return to the Summary Table.
Configuration of DIO5
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO5 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG6 is shown in Table 15-48.
Return to the Summary Table.
Configuration of DIO6
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO6 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG7 is shown in Table 15-49.
Return to the Summary Table.
Configuration of DIO7
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO7 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG8 is shown in Table 15-50.
Return to the Summary Table.
Configuration of DIO8
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO8 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG9 is shown in Table 15-51.
Return to the Summary Table.
Configuration of DIO9
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO9 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG10 is shown in Table 15-52.
Return to the Summary Table.
Configuration of DIO10
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO10 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG11 is shown in Table 15-53.
Return to the Summary Table.
Configuration of DIO11
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO11 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG12 is shown in Table 15-54.
Return to the Summary Table.
Configuration of DIO12
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO12 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG13 is shown in Table 15-55.
Return to the Summary Table.
Configuration of DIO13
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO13 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG14 is shown in Table 15-56.
Return to the Summary Table.
Configuration of DIO14
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO14 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG15 is shown in Table 15-57.
Return to the Summary Table.
Configuration of DIO15
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO15 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG16 is shown in Table 15-58.
Return to the Summary Table.
Configuration of DIO16
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO16 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG17 is shown in Table 15-59.
Return to the Summary Table.
Configuration of DIO17
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO17 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG18 is shown in Table 15-60.
Return to the Summary Table.
Configuration of DIO18
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO18 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG19 is shown in Table 15-61.
Return to the Summary Table.
Configuration of DIO19
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO19 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG20 is shown in Table 15-62.
Return to the Summary Table.
Configuration of DIO20
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO20 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG21 is shown in Table 15-63.
Return to the Summary Table.
Configuration of DIO21
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO21 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG22 is shown in Table 15-64.
Return to the Summary Table.
Configuration of DIO22
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO22 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG23 is shown in Table 15-65.
Return to the Summary Table.
Configuration of DIO23
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO23 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG24 is shown in Table 15-66.
Return to the Summary Table.
Configuration of DIO24
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO24 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG25 is shown in Table 15-67.
Return to the Summary Table.
Configuration of DIO25
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO25 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG26 is shown in Table 15-68.
Return to the Summary Table.
Configuration of DIO26
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO26 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG27 is shown in Table 15-69.
Return to the Summary Table.
Configuration of DIO27
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO27 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG28 is shown in Table 15-70.
Return to the Summary Table.
Configuration of DIO28
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO28 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG29 is shown in Table 15-71.
Return to the Summary Table.
Configuration of DIO29
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO29 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG30 is shown in Table 15-72.
Return to the Summary Table.
Configuration of DIO30
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO30 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG31 is shown in Table 15-73.
Return to the Summary Table.
Configuration of DIO31
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO31 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 8h = AUX IO 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG32 is shown in Table 15-74.
Return to the Summary Table.
Configuration of DIO32
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO32 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG33 is shown in Table 15-75.
Return to the Summary Table.
Configuration of DIO33
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO33 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG34 is shown in Table 15-76.
Return to the Summary Table.
Configuration of DIO34
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO34 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG35 is shown in Table 15-77.
Return to the Summary Table.
Configuration of DIO35
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO35 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG36 is shown in Table 15-78.
Return to the Summary Table.
Configuration of DIO36
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO36 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG37 is shown in Table 15-79.
Return to the Summary Table.
Configuration of DIO37
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO37 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG38 is shown in Table 15-80.
Return to the Summary Table.
Configuration of DIO38
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO38 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG39 is shown in Table 15-81.
Return to the Summary Table.
Configuration of DIO39
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO39 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG40 is shown in Table 15-82.
Return to the Summary Table.
Configuration of DIO40
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO40 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG41 is shown in Table 15-83.
Return to the Summary Table.
Configuration of DIO41
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO41 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG42 is shown in Table 15-84.
Return to the Summary Table.
Configuration of DIO42
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO42 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG43 is shown in Table 15-85.
Return to the Summary Table.
Configuration of DIO43
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-18 | RESERVED | R | 0h | Reserved |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO43 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG44 is shown in Table 15-86.
Return to the Summary Table.
Configuration of DIO44
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO44 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG45 is shown in Table 15-87.
Return to the Summary Table.
Configuration of DIO45
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO45 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG46 is shown in Table 15-88.
Return to the Summary Table.
Configuration of DIO46
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO46 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |
IOCFG47 is shown in Table 15-89.
Return to the Summary Table.
Configuration of DIO47
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IOEV_MCU_WU_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert MCU_WU event 1: Input edge detection asserts MCU_WU event |
30 | HYST_EN | R/W | 0h | 0: Input hysteresis disable 1: Input hysteresis enable |
29 | IE | R/W | 0h | 0: Input disabled 1: Input enabled Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be ignored. |
28-27 | WU_CFG | R/W | 0h | If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or >0x08: 00: No wake-up 01: No wake-up 10: Wakes up from shutdown if this pad is going low. 11: Wakes up from shutdown if this pad is going high. If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, this register only sets wakeup enable or not. 00, 01: Wakeup disabled 10, 11: Wakeup enabled Polarity is controlled from AON registers. Note:When the MSB is set, the IOC will deactivate the output enable for the DIO. |
26-24 | IOMODE | R/W | 0h | IO Mode Not applicable for IO configured for AON periph. signals and AUX PORT_ID 0x01-0x08 AUX has its own open_source/drain configuration. 0x2: Reserved. Undefined behavior. 0x3: Reserved. Undefined behavior. 0h = NORMAL : Normal input / output 1h = INV : Inverted input / ouput 4h = OPENDR : Open Drain, Normal input / output 5h = OPENDR_INV : Open Drain Inverted input / output 6h = OPENSRC : Open Source Normal input / output 7h = OPENSRC_INV : Open Source Inverted input / output |
23 | IOEV_AON_PROG2_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG2 event 1: Input edge detection asserts AON_PROG2 event |
22 | IOEV_AON_PROG1_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG1 event 1: Input edge detection asserts AON_PROG1 event |
21 | IOEV_AON_PROG0_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert AON_PROG0 event 1: Input edge detection asserts AON_PROG0 event |
20-19 | RESERVED | R | 0h | Reserved |
18 | EDGE_IRQ_EN | R/W | 0h | 0: No interrupt generation 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is enabled) |
17-16 | EDGE_DET | R/W | 0h | Enable generation of edge detection events on this IO
0h = NONE : No edge detection 1h = Negative edge detection 2h = Positive edge detection 3h = Positive and negative edge detection |
15-14 | PULL_CTL | R/W | 3h | Pull control
1h = DWN : Pull down 2h = UP : Pull up 3h = DIS : No pull |
13 | SLEW_RED | R/W | 0h | 0: Normal slew rate 1: Enables reduced slew rate in output driver. |
12-11 | IOCURR | R/W | 0h | Selects IO current mode of this IO.
0h = 2MA : Low-Current (LC) mode: Min 2 mA when IOSTR is set to AUTO 1h = 4MA : High-Current (HC) mode: Min 4 mA when IOSTR is set to AUTO 2h = 4_8MA : Extended-Current (EC) mode: Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when IOSTR is set to AUTO |
10-9 | IOSTR | R/W | 0h | Select source for drive strength control of this IO. This setting controls the drive strength of the Low-Current (LC) mode. Higher drive strength can be selected in IOCURR 0h = Automatic drive strength, controlled by AON BATMON based on battery voltage. (min 2 mA @VDDS) 1h = Minimum drive strength, controlled by AON_IOC:IOSTRMIN (min 2 mA @3.3V with default values) 2h = MED : Medium drive strength, controlled by AON_IOC:IOSTRMED (min 2 mA @2.5V with default values) 3h = Maximum drive strength, controlled by AON_IOC:IOSTRMAX (min 2 mA @1.8V with default values) |
8 | IOEV_RTC_EN | R/W | 0h | Event asserted by this IO when edge detection is enabled 0: Input edge detection does not assert RTC event 1: Input edge detection asserts RTC event |
7 | RESERVED | R | 0h | Reserved |
6-0 | PORT_ID | R/W | 0h | Selects usage for DIO47 Note: This field should not be written other than the times when PORT_ID value is specifically required to change. 0h = General Purpose IO 7h = AON 32 KHz clock (SCLK_LF) 9h = SPI0_RX : SPI0 RX Ah = SPI0_TX : SPI0 TX Bh = SPI0_CS : SPI0 CS Ch = SPI0_CLK : SPI0 CLK Dh = I2C0_MSSDA : I2C0 Data Eh = I2C0_MSSCL : I2C0 Clock Fh = UART0_RX : UART0 RX 10h = UART0_TX : UART0 TX 11h = UART0_CTS : UART0 CTS 12h = UART0_RTS : UART0 RTS 13h = UART1_RX : UART1 RX 14h = UART1_TX : UART1 TX 15h = UART1_CTS : UART1 CTS 16h = UART1_RTS : UART1 RTS 17h = PORT_EVENT0 : PORT EVENT 0 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 18h = PORT_EVENT1 : PORT EVENT 1 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 19h = PORT_EVENT2 : PORT EVENT 2 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ah = PORT_EVENT3 : PORT EVENT 3 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Bh = PORT_EVENT4 : PORT EVENT 4 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Ch = PORT_EVENT5 : PORT EVENT 5 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Dh = PORT_EVENT6 : PORT EVENT 6 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 1Eh = PORT_EVENT7 : PORT EVENT 7 Can be used as a general purpose IO event by selecting it through registers in the EVENT module, for example EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, and so on 20h = CPU_SWV : CPU SWV 21h = SPI1_RX : SPI1 RX 22h = SPI1_TX : SPI1 TX 23h = SPI1_CS : SPI1 CS 24h = SPI1_CLK : SPI1 CLK 25h = I2S_AD0 : I2S Data 0 26h = I2S_AD1 : I2S Data 1 27h = I2S_WCLK : I2S WCLK 28h = I2S_BCLK : I2S BCLK 29h = I2S_MCLK : I2S MCLK 2Eh = RF Core Trace 2Fh = RF Core Data Out 0 30h = RF Core Data Out 1 31h = RF Core Data Out 2 32h = RF Core Data Out 3 33h = RF Core Data In 0 34h = RF Core Data In 1 35h = RF Core SMI Data Link Out 36h = RF Core SMI Data Link In 37h = RF Core SMI Command Link Out 38h = RF Core SMI Command Link In 39h = SPI2_RX : SPI2 RX 3Ah = SPI2_TX : SPI2 TX 3Bh = SPI2_CS : SPI2 CS 3Ch = SPI2_CLK : SPI2 CLK 3Dh = SPI3_RX : SPI3 RX 3Eh = SPI3_TX : SPI3 TX 3Fh = SPI3_CS : SPI3 CS 40h = SPI3_CLK : SPI3 CLK 41h = UART2_RX : UART2 RX 42h = UART2_TX : UART2 TX 43h = UART2_CTS : UART2 CTS 44h = UART2_RTS : UART2 RTS 45h = UART3_RX : UART3 RX 46h = UART3_TX : UART3 TX 47h = UART3_CTS : UART3 CTS 48h = UART3_RTS : UART3 RTS 49h = I2C1_MSSDA : I2C1 Data 4Ah = I2C1_MSSCL : I2C1 Clock |