SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 7-8 lists the memory-mapped registers for the PRCM registers. All register offset addresses not listed in Table 7-8 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | INFRCLKDIVR | Infrastructure Clock Division Factor For Run Mode | Section 7.8.1.1 |
4h | INFRCLKDIVS | Infrastructure Clock Division Factor For Sleep Mode | Section 7.8.1.2 |
8h | INFRCLKDIVDS | Infrastructure Clock Division Factor For DeepSleep Mode | Section 7.8.1.3 |
Ch | VDCTL | MCU Voltage Domain Control | Section 7.8.1.4 |
28h | CLKLOADCTL | Load PRCM Settings To CLKCTRL Power Domain | Section 7.8.1.5 |
2Ch | RFCCLKG | RFC Clock Gate | Section 7.8.1.6 |
30h | VIMSCLKG | VIMS Clock Gate | Section 7.8.1.7 |
3Ch | SECDMACLKGR | SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes | Section 7.8.1.8 |
40h | SECDMACLKGS | SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode | Section 7.8.1.9 |
44h | SECDMACLKGDS | SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode | Section 7.8.1.10 |
48h | GPIOCLKGR | GPIO Clock Gate For Run And All Modes | Section 7.8.1.11 |
4Ch | GPIOCLKGS | GPIO Clock Gate For Sleep Mode | Section 7.8.1.12 |
50h | GPIOCLKGDS | GPIO Clock Gate For Deep Sleep Mode | Section 7.8.1.13 |
54h | GPTCLKGR | GPT Clock Gate For Run And All Modes | Section 7.8.1.14 |
58h | GPTCLKGS | GPT Clock Gate For Sleep Mode | Section 7.8.1.15 |
5Ch | GPTCLKGDS | GPT Clock Gate For Deep Sleep Mode | Section 7.8.1.16 |
60h | I2CCLKGR | I2C Clock Gate For Run And All Modes | Section 7.8.1.17 |
64h | I2CCLKGS | I2C Clock Gate For Sleep Mode | Section 7.8.1.18 |
68h | I2CCLKGDS | I2C Clock Gate For Deep Sleep Mode | Section 7.8.1.19 |
6Ch | UARTCLKGR | UART Clock Gate For Run And All Modes | Section 7.8.1.20 |
70h | UARTCLKGS | UART Clock Gate For Sleep Mode | Section 7.8.1.21 |
74h | UARTCLKGDS | UART Clock Gate For Deep Sleep Mode | Section 7.8.1.22 |
78h | SPICLKGR | SPI Clock Gate For Run And All Modes | Section 7.8.1.23 |
7Ch | SPICLKGS | SPI Clock Gate For Sleep Mode | Section 7.8.1.24 |
80h | SPICLKGDS | SPI Clock Gate For Deep Sleep Mode | Section 7.8.1.25 |
84h | I2SCLKGR | I2S Clock Gate For Run And All Modes | Section 7.8.1.26 |
88h | I2SCLKGS | I2S Clock Gate For Sleep Mode | Section 7.8.1.27 |
8Ch | I2SCLKGDS | I2S Clock Gate For Deep Sleep Mode | Section 7.8.1.28 |
B4h | SYSBUSCLKDIV | Internal | Section 7.8.1.29 |
B8h | CPUCLKDIV | Internal | Section 7.8.1.30 |
BCh | PERBUSCPUCLKDIV | Internal | Section 7.8.1.31 |
C4h | PERDMACLKDIV | Internal | Section 7.8.1.32 |
C8h | I2SBCLKSEL | I2S Clock Control | Section 7.8.1.33 |
CCh | GPTCLKDIV | GPT Scalar | Section 7.8.1.34 |
D0h | I2SCLKCTL | I2S Clock Control | Section 7.8.1.35 |
D4h | I2SMCLKDIV | MCLK Division Ratio | Section 7.8.1.36 |
D8h | I2SBCLKDIV | BCLK Division Ratio | Section 7.8.1.37 |
DCh | I2SWCLKDIV | WCLK Division Ratio | Section 7.8.1.38 |
F0h | RESETSECDMA | RESET For SEC (PKA And TRNG And CRYPTO) And UDMA | Section 7.8.1.39 |
F4h | RESETGPIO | RESET For GPIO IPs | Section 7.8.1.40 |
F8h | RESETGPT | RESET For GPT Ips | Section 7.8.1.41 |
FCh | RESETI2C | RESET For I2C IPs | Section 7.8.1.42 |
100h | RESETUART | RESET For UART IPs | Section 7.8.1.43 |
104h | RESETSPI | RESET For SPI IPs | Section 7.8.1.44 |
108h | RESETI2S | RESET For I2S IP | Section 7.8.1.45 |
12Ch | PDCTL0 | Power Domain Control | Section 7.8.1.46 |
130h | PDCTL0RFC | RFC Power Domain Control | Section 7.8.1.47 |
134h | PDCTL0SERIAL | SERIAL Power Domain Control | Section 7.8.1.48 |
138h | PDCTL0PERIPH | PERIPH Power Domain Control | Section 7.8.1.49 |
140h | PDSTAT0 | Power Domain Status | Section 7.8.1.50 |
144h | PDSTAT0RFC | RFC Power Domain Status | Section 7.8.1.51 |
148h | PDSTAT0SERIAL | SERIAL Power Domain Status | Section 7.8.1.52 |
14Ch | PDSTAT0PERIPH | PERIPH Power Domain Status | Section 7.8.1.53 |
17Ch | PDCTL1 | Power Domain Control | Section 7.8.1.54 |
184h | PDCTL1CPU | CPU Power Domain Direct Control | Section 7.8.1.55 |
188h | PDCTL1RFC | RFC Power Domain Direct Control | Section 7.8.1.56 |
18Ch | PDCTL1VIMS | VIMS Mode Direct Control | Section 7.8.1.57 |
194h | PDSTAT1 | Power Manager Status | Section 7.8.1.58 |
198h | PDSTAT1BUS | BUS Power Domain Direct Read Status | Section 7.8.1.59 |
19Ch | PDSTAT1RFC | RFC Power Domain Direct Read Status | Section 7.8.1.60 |
1A0h | PDSTAT1CPU | CPU Power Domain Direct Read Status | Section 7.8.1.61 |
1A4h | PDSTAT1VIMS | VIMS Mode Direct Read Status | Section 7.8.1.62 |
1CCh | RFCBITS | Control To RFC | Section 7.8.1.63 |
1D0h | RFCMODESEL | Selected RFC Mode | Section 7.8.1.64 |
1D4h | RFCMODEHWOPT | Allowed RFC Modes | Section 7.8.1.65 |
1E0h | PWRPROFSTAT | Power Profiler Register | Section 7.8.1.66 |
21Ch | MCUSRAMCFG | MCU SRAM configuration | Section 7.8.1.67 |
224h | RAMRETEN | Memory Retention Control | Section 7.8.1.68 |
290h | OSCIMSC | Oscillator Interrupt Mask Control | Section 7.8.1.69 |
294h | OSCRIS | Oscillator Raw Interrupt Status | Section 7.8.1.70 |
298h | OSCICR | Oscillator Raw Interrupt Clear | Section 7.8.1.71 |
2B0h | NVMNSCADDR | NVM Non-Secure Callable boundary Address | Section 7.8.1.72 |
2B4h | NVMNSADDR | NVM Non-Secure boundary Address | Section 7.8.1.73 |
2B8h | SRAMNSCADDR | SRAM Non-Secure Callable boundary Address | Section 7.8.1.74 |
2BCh | SRAMNSADDR | SRAM Non-Secure Callable boundary Address | Section 7.8.1.75 |
2C0h | BUSSECCFG | BUS Security Configuration Register | Section 7.8.1.76 |
2C4h | CPULOCK | CPU Lock Register | Section 7.8.1.77 |
Complex bit access types are encoded to fit into small table cells. Table 7-9 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
INFRCLKDIVR is shown in Table 7-10.
Return to the Summary Table.
Infrastructure Clock Division Factor For Run Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | RATIO | R/W | 0h | Division rate for clocks driving modules in the MCU_AON domain when system CPU is in run mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 |
INFRCLKDIVS is shown in Table 7-11.
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Infrastructure Clock Division Factor For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | RATIO | R/W | 0h | Division rate for clocks driving modules in the MCU_AON domain when system CPU is in sleep mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 |
INFRCLKDIVDS is shown in Table 7-12.
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Infrastructure Clock Division Factor For DeepSleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | RATIO | R/W | 0h | Division rate for clocks driving modules in the MCU_AON domain when system CPU is in deepsleep mode. Division ratio affects both infrastructure clock and perbusull clock.
0h = Divide by 1 1h = Divide by 2 2h = Divide by 8 3h = Divide by 32 |
VDCTL is shown in Table 7-13.
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MCU Voltage Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ULDO | R/W | 0h | Request PMCTL to switch to uLDO. 0: No request 1: Assert request when possible The bit will have no effect before the following requirements are met: 1. PDCTL1.CPU_ON = 0 2. PDCTL1.VIMS_MODE = x0 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be loaded with CLKLOADCTL.LOAD) 6. RFC do no request access to BUS 7. System CPU in deepsleep |
CLKLOADCTL is shown in Table 7-14.
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Load PRCM Settings To CLKCTRL Power Domain
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | LOAD_DONE | R | 1h | Status of LOAD. Will be cleared to 0 when any of the registers requiring a LOAD is written to, and be set to 1 when a LOAD is done. Note that writing no change to a register will result in the LOAD_DONE being cleared. 0 : One or more registers have been write accessed after last LOAD 1 : No registers are write accessed after last LOAD |
0 | LOAD | W | 0h | 0: No action 1: Load settings to CLKCTRL. Bit is HW cleared. Multiple changes to settings may be done before LOAD is written once so all changes takes place at the same time. LOAD can also be done after single setting updates. Registers that needs to be followed by LOAD before settings being applied are: - SYSBUSCLKDIV - CPUCLKDIV - PERBUSCPUCLKDIV - PERDMACLKDIV - PERBUSCPUCLKG - RFCCLKG - VIMSCLKG - SECDMACLKGR - SECDMACLKGS - SECDMACLKGDS - GPIOCLKGR - GPIOCLKGS - GPIOCLKGDS - GPTCLKGR - GPTCLKGS - GPTCLKGDS - GPTCLKDIV - I2CCLKGR - I2CCLKGS - I2CCLKGDS - SPICLKGR - SPICLKGS - SPICLKGDS - UARTCLKGR - UARTCLKGS - UARTCLKGDS - I2SCLKGR - I2SCLKGS - I2SCLKGDS - I2SBCLKSEL - I2SCLKCTL - I2SMCLKDIV - I2SBCLKDIV - I2SWCLKDIV - MCUSRAMCFG |
RFCCLKG is shown in Table 7-15.
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RFC Clock Gate
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 1h | 0: Disable Clock 1: Enable clock if RFC power domain is on For changes to take effect, CLKLOADCTL.LOAD needs to be written |
VIMSCLKG is shown in Table 7-16.
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VIMS Clock Gate
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | CLK_EN | R/W | 3h | 00: Disable clock 01: Disable clock when SYSBUS clock is disabled 11: Enable clock For changes to take effect, CLKLOADCTL.LOAD needs to be written |
SECDMACLKGR is shown in Table 7-17.
Return to the Summary Table.
SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | DMA_AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written |
23-20 | RESERVED | R | 0h | Reserved |
19 | PKA_ZERIOZE_RESET_N | R/W | 0h | Zeroization logic hardware reset. 0: pka_zeroize logic inactive. 1: pka_zeroize of memory is enabled. This register must remain active until the memory are completely zeroized which requires 256 periods on systembus clock. |
18 | PKA_AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
17 | TRNG_AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
16 | CRYPTO_AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and SECDMACLKGDS.CRYPTO_CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written |
15-9 | RESERVED | R | 0h | Reserved |
8 | DMA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
7-3 | RESERVED | R | 0h | Reserved |
2 | PKA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
1 | TRNG_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
0 | CRYPTO_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
SECDMACLKGS is shown in Table 7-18.
Return to the Summary Table.
SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | DMA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
7-3 | RESERVED | R | 0h | Reserved |
2 | PKA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
1 | TRNG_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
0 | CRYPTO_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
SECDMACLKGDS is shown in Table 7-19.
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SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | DMA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
7-3 | RESERVED | R | 0h | Reserved |
2 | PKA_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
1 | TRNG_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
0 | CRYPTO_CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
GPIOCLKGR is shown in Table 7-20.
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GPIO Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
7-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
GPIOCLKGS is shown in Table 7-21.
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GPIO Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
GPIOCLKGDS is shown in Table 7-22.
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GPIO Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by GPIOCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
GPTCLKGR is shown in Table 7-23.
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GPT Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | AM_CLK_EN | R/W | 0h | Each bit below has the following meaning: 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 in all modes 2h = Enable clock for GPT1 in all modes 4h = Enable clock for GPT2 in all modes 8h = Enable clock for GPT3 in all modes |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 |
GPTCLKGS is shown in Table 7-24.
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GPT Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by GPTCLKGR.AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 |
GPTCLKGDS is shown in Table 7-25.
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GPT Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | Each bit below has the following meaning: 0: Disable clock 1: Enable clock Can be forced on by GPTCLKGR.AM_CLK_EN ENUMs can be combined For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for GPT0 2h = Enable clock for GPT1 4h = Enable clock for GPT2 8h = Enable clock for GPT3 |
I2CCLKGR is shown in Table 7-26.
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I2C Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-8 | AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for I2C0 2h = Enable clock for I2C1 |
7-2 | RESERVED | R | 0h | Reserved |
1-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for I2C0 2h = Enable clock for I2C1 |
I2CCLKGS is shown in Table 7-27.
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I2C Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for I2C0 2h = Enable clock for I2C1 |
I2CCLKGDS is shown in Table 7-28.
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I2C Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | RESERVED | R/W | 0h | |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by I2CCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for I2C0 2h = Enable clock for I2C1 |
UARTCLKGR is shown in Table 7-29.
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UART Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1 4h = Enable clock for UART2 8h = Enable clock for UART3 |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1 4h = Enable clock for UART2 8h = Enable clock for UART3 |
UARTCLKGS is shown in Table 7-30.
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UART Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by UARTCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1 4h = Enable clock for UART2 8h = Enable clock for UART3 |
UARTCLKGDS is shown in Table 7-31.
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UART Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by UARTCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for UART0 2h = Enable clock for UART1 4h = Enable clock for UART2 8h = Enable clock for UART3 |
SPICLKGR is shown in Table 7-32.
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SPI Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11-8 | AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, SPICLKGS.CLK_EN and SPICLKGDS.CLK_EN when enabled. For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SPI0 2h = Enable clock for SPI1 4h = Enable clock for SPI2 8h = Enable clock for SPI3 |
7-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SPI0 2h = Enable clock for SPI1 4h = Enable clock for SPI2 8h = Enable clock for SPI3 |
SPICLKGS is shown in Table 7-33.
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SPI Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SPICLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SPI0 2h = Enable clock for SPI1 4h = Enable clock for SPI2 8h = Enable clock for SPI3 |
SPICLKGDS is shown in Table 7-34.
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SPI Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by SPICLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written 1h = Enable clock for SPI0 2h = Enable clock for SPI1 4h = Enable clock for SPI2 8h = Enable clock for SPI3 |
I2SCLKGR is shown in Table 7-35.
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I2S Clock Gate For Run And All Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | AM_CLK_EN | R/W | 0h | 0: No force 1: Force clock on for all modes (Run, Sleep and Deep Sleep) Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. SYSBUS clock will always run when enabled For changes to take effect, CLKLOADCTL.LOAD needs to be written |
7-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
I2SCLKGS is shown in Table 7-36.
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I2S Clock Gate For Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
I2SCLKGDS is shown in Table 7-37.
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I2S Clock Gate For Deep Sleep Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CLK_EN | R/W | 0h | 0: Disable clock 1: Enable clock SYSBUS clock will always run when enabled Can be forced on by I2SCLKGR.AM_CLK_EN For changes to take effect, CLKLOADCTL.LOAD needs to be written |
SYSBUSCLKDIV is shown in Table 7-38.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | RATIO | R/W | 0h | Internal. Only to be used through TI provided API. |
CPUCLKDIV is shown in Table 7-39.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RATIO | R/W | 0h | Internal. Only to be used through TI provided API. |
PERBUSCPUCLKDIV is shown in Table 7-40.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | RATIO | R/W | 0h | Internal. Only to be used through TI provided API. |
PERDMACLKDIV is shown in Table 7-41.
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Internal. Only to be used through TI provided API.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | RATIO | R/W | 0h | Internal. Only to be used through TI provided API. |
I2SBCLKSEL is shown in Table 7-42.
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I2S Clock Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | SRC | R/W | 0h | BCLK source selector 0: Use external BCLK 1: Use internally generated clock For changes to take effect, CLKLOADCTL.LOAD needs to be written |
GPTCLKDIV is shown in Table 7-43.
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GPT Scalar
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-0 | RATIO | R/W | 0h | Scalar used for GPTs. The division rate will be constant and ungated for Run / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD needs to be written Other values are not supported.
0h = Divide by 1 1h = Divide by 2 2h = Divide by 4 3h = Divide by 8 4h = Divide by 16 5h = Divide by 32 6h = Divide by 64 7h = Divide by 128 8h = Divide by 256 |
I2SCLKCTL is shown in Table 7-44.
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I2S Clock Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | SMPL_ON_POSEDGE | R/W | 0h | On the I2S serial interface, data and WCLK is sampled and clocked out on opposite edges of BCLK. 0 - data and WCLK are sampled on the negative edge and clocked out on the positive edge. 1 - data and WCLK are sampled on the positive edge and clocked out on the negative edge. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
2-1 | WCLK_PHASE | R/W | 0h | Decides how the WCLK division ratio is calculated and used to generate different duty cycles (See I2SWCLKDIV.WDIV). 0: Single phase 1: Dual phase 2: User Defined 3: Reserved/Undefined For changes to take effect, CLKLOADCTL.LOAD needs to be written |
0 | EN | R/W | 0h | 0: MCLK, BCLK and WCLK will be static low 1: Enables the generation of MCLK, BCLK and WCLK For changes to take effect, CLKLOADCTL.LOAD needs to be written |
I2SMCLKDIV is shown in Table 7-45.
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MCLK Division Ratio
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-0 | MDIV | R/W | 0h | An unsigned factor of the division ratio used to generate MCLK [2-1024]: MCLK = MCUCLK/MDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If MDIV is odd the low phase of the clock is one MCUCLK period longer than the high phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
I2SBCLKDIV is shown in Table 7-46.
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BCLK Division Ratio
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9-0 | BDIV | R/W | 0h | An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: BCLK = MCUCLK/BDIV[Hz] MCUCLK is 48MHz. A value of 0 is interpreted as 1024. A value of 1 is invalid. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock is one MCUCLK period longer than the high phase. If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the clock is one MCUCLK period longer than the low phase. For changes to take effect, CLKLOADCTL.LOAD needs to be written |
I2SWCLKDIV is shown in Table 7-47.
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WCLK Division Ratio
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | WDIV | R/W | 0h | If I2SCLKCTL.WCLK_PHASE = 0, Single phase. WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] MCUCLK is 48MHz. If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK periods. WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] If I2SCLKCTL.WCLK_PHASE = 2, User defined. WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] (unsigned, [1-255]) BCLK periods. WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] For changes to take effect, CLKLOADCTL.LOAD needs to be written |
RESETSECDMA is shown in Table 7-48.
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RESET For SEC (PKA And TRNG And CRYPTO) And UDMA
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | 0h | Reserved |
8 | DMA | W | 0h | Write 1 to reset. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
7-3 | RESERVED | R | 0h | Reserved |
2 | PKA | W | 0h | Write 1 to reset. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
1 | TRNG | W | 0h | Write 1 to reset. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
0 | CRYPTO | W | 0h | Write 1 to reset. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETGPIO is shown in Table 7-49.
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RESET For GPIO IPs
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | GPIO | W | 0h | 0: No action 1: Reset GPIO. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETGPT is shown in Table 7-50.
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RESET For GPT Ips
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | GPT | W | 0h | 0: No action 1: Reset all GPTs. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETI2C is shown in Table 7-51.
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RESET For I2C IPs
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | I2C1 | W | 0h | 0: No action 1: Reset I2C1. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
0 | I2C0 | W | 0h | 0: No action 1: Reset I2C0. HW cleared. Access will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETUART is shown in Table 7-52.
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RESET For UART IPs
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | UART3 | W | 0h | 0: No action 1: Reset UART3. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
2 | UART2 | W | 0h | 0: No action 1: Reset UART2. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
1 | UART1 | W | 0h | 0: No action 1: Reset UART1. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
0 | UART0 | W | 0h | 0: No action 1: Reset UART0. HW cleared. Access will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETSPI is shown in Table 7-53.
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RESET For SPI IPs
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | SPI3 | W | 0h | 0: No action 1: Reset SPI3. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
2 | SPI2 | W | 0h | 0: No action 1: Reset SPI2. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
1 | SPI1 | W | 0h | 0: No action 1: Reset SPI1. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
0 | SPI0 | W | 0h | 0: No action 1: Reset SPI0. HW cleared. Access will only have effect when SERIAL power domain is on, PDSTAT0.SERIAL_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
RESETI2S is shown in Table 7-54.
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RESET For I2S IP
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | I2S | W | 0h | 0: No action 1: Reset module. HW cleared. Access will only have effect when PERIPH power domain is on, PDSTAT0.PERIPH_ON = 1 Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not activated while executing from flash. This means one cannot execute from flash when using the SW reset. |
PDCTL0 is shown in Table 7-55.
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Power Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | PERIPH_ON | R/W | 0h | PERIPH Power domain. 0: PERIPH power domain is powered down 1: PERIPH power domain is powered up |
1 | SERIAL_ON | R/W | 0h | SERIAL Power domain. 0: SERIAL power domain is powered down 1: SERIAL power domain is powered up |
0 | RFC_ON | R/W | 0h | 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1: RFC power domain powered on |
PDCTL0RFC is shown in Table 7-56.
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RFC Power Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R/W | 0h | Alias for PDCTL0.RFC_ON |
PDCTL0SERIAL is shown in Table 7-57.
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SERIAL Power Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R/W | 0h | Alias for PDCTL0.SERIAL_ON |
PDCTL0PERIPH is shown in Table 7-58.
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PERIPH Power Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R/W | 0h | Alias for PDCTL0.PERIPH_ON |
PDSTAT0 is shown in Table 7-59.
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Power Domain Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2 | PERIPH_ON | R | 0h | PERIPH Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed) |
1 | SERIAL_ON | R | 0h | SERIAL Power domain. 0: Domain may be powered down 1: Domain powered up (guaranteed) |
0 | RFC_ON | R | 0h | RFC Power domain 0: Domain may be powered down 1: Domain powered up (guaranteed) |
PDSTAT0RFC is shown in Table 7-60.
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RFC Power Domain Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 0h | Alias for PDSTAT0.RFC_ON |
PDSTAT0SERIAL is shown in Table 7-61.
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SERIAL Power Domain Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 0h | Alias for PDSTAT0.SERIAL_ON |
PDSTAT0PERIPH is shown in Table 7-62.
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PERIPH Power Domain Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 0h | Alias for PDSTAT0.PERIPH_ON |
PDCTL1 is shown in Table 7-63.
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Power Domain Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4-3 | VIMS_MODE | R/W | 1h | 00: VIMS power domain is only powered when CPU power domain is powered. 01: VIMS power domain is powered whenever the BUS power domain is powered. 1X: Block power up of VIMS power domain at next wake up. This mode only has effect when VIMS power domain is not powered. Used for Autonomous RF Core. |
2 | RFC_ON | R/W | 0h | 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power domain powered on Bit shall be used by RFC in autonomous mode but there is no HW restrictions from system CPU to access the bit. |
1 | CPU_ON | R/W | 1h | 0: Causes a power down of the CPU power domain when system CPU indicates it is idle. 1: Initiates power-on of the CPU power domain. This bit is automatically set by a WIC power-on event. |
0 | RESERVED | R | 0h | Reserved |
PDCTL1CPU is shown in Table 7-64.
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CPU Power Domain Direct Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R/W | 1h | This is an alias for PDCTL1.CPU_ON |
PDCTL1RFC is shown in Table 7-65.
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RFC Power Domain Direct Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R/W | 0h | This is an alias for PDCTL1.RFC_ON |
PDCTL1VIMS is shown in Table 7-66.
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VIMS Mode Direct Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1-0 | MODE | R/W | 1h | This is an alias for PDCTL1.VIMS_MODE |
PDSTAT1 is shown in Table 7-67.
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Power Manager Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Reserved |
4 | BUS_ON | R | 1h | 0: BUS domain not accessible 1: BUS domain is currently accessible |
3 | VIMS_ON | R | 1h | 0: VIMS domain not accessible 1: VIMS domain is currently accessible |
2 | RFC_ON | R | 0h | 0: RFC domain not accessible 1: RFC domain is currently accessible |
1 | CPU_ON | R | 1h | 0: CPU and BUS domain not accessible 1: CPU and BUS domains are both currently accessible |
0 | RESERVED | R | 0h | Reserved |
PDSTAT1BUS is shown in Table 7-68.
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BUS Power Domain Direct Read Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 1h | This is an alias for PDSTAT1.BUS_ON |
PDSTAT1RFC is shown in Table 7-69.
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RFC Power Domain Direct Read Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 0h | This is an alias for PDSTAT1.RFC_ON |
PDSTAT1CPU is shown in Table 7-70.
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CPU Power Domain Direct Read Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 1h | This is an alias for PDSTAT1.CPU_ON |
PDSTAT1VIMS is shown in Table 7-71.
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VIMS Mode Direct Read Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | ON | R | 1h | This is an alias for PDSTAT1.VIMS_ON |
RFCBITS is shown in Table 7-72.
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Control To RFC
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | READ | R/W | 0h | Control bits for RFC. The RF core CPE processor will automatically check this register when it boots, and it can be used to immediately instruct CPE to perform some tasks at its start-up. The supported functionality is ROM-defined and may vary. See the technical reference manual for more details. |
RFCMODESEL is shown in Table 7-73.
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Selected RFC Mode
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R | 0h | Reserved |
2-0 | CURR | R/W | 0h | Selects the set of commands that the RFC will accept. Only modes permitted by RFCMODEHWOPT.AVAIL are writable. See the technical reference manual for details.
0h = Select Mode 0 1h = Select Mode 1 2h = Select Mode 2 3h = Select Mode 3 4h = Select Mode 4 5h = Select Mode 5 6h = Select Mode 6 7h = Select Mode 7 |
RFCMODEHWOPT is shown in Table 7-74.
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Allowed RFC Modes
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | AVAIL | R | 0h | Permitted RFC modes. More than one mode can be permitted.
1h = Mode 0 permitted 2h = Mode 1 permitted 4h = Mode 2 permitted 8h = Mode 3 permitted 10h = Mode 4 permitted 20h = Mode 5 permitted 40h = Mode 6 permitted 80h = Mode 7 permitted |
PWRPROFSTAT is shown in Table 7-75.
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Power Profiler Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | VALUE | R/W | 1h | SW can use these bits to timestamp the application. These bits are also available through the testtap and can thus be used by the emulator to profile in real time. |
MCUSRAMCFG is shown in Table 7-76.
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MCU SRAM configuration
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | 0h | Reserved |
6 | PARITY_EN | R/W | 0h | Parity enable 0: Parity disabled Parity section available as GPRAM 1: Parity enabled |
5 | BM_OFF | R/W | 1h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
4 | PAGE | R/W | 0h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
3 | PGS | R/W | 0h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
2 | BM | R/W | 0h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
1 | PCH_F | R/W | 0h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
0 | PCH_L | R/W | 0h | NOT in use. Writing any other value than the reset value may result in undefined behavior. |
RAMRETEN is shown in Table 7-77.
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Memory Retention Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RFCULL | R/W | 1h | 0: Retention for RFC ULL SRAM disabled 1: Retention for RFC ULL SRAM enabled Memories controlled: CPEULLRAM |
2 | RFC | R/W | 0h | 0: Retention for RFC SRAM disabled 1: Retention for RFC SRAM enabled Memories controlled: CPERAM MCERAM RFERAM DSBRAM |
1-0 | VIMS | R/W | 3h | 0: Memory retention disabled 1: Memory retention enabled Bit 0: VIMS_TRAM Bit 1: VIMS_CRAM Legal modes depend on settings in VIMS:CTL.MODE 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to CACHE or SPLIT mode after waking up again 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in GPRAM mode after wake up, alternatively select OFF mode first and then CACHE or SPLIT mode. 10: Illegal mode 11: No restrictions |
OSCIMSC is shown in Table 7-78.
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Oscillator Interrupt Mask Control
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | HFSRCPENDIM | R/W | 0h | 0: Disable interrupt generation when HFSRCPEND is qualified 1: Enable interrupt generation when HFSRCPEND is qualified |
6 | LFSRCDONEIM | R/W | 0h | 0: Disable interrupt generation when LFSRCDONE is qualified 1: Enable interrupt generation when LFSRCDONE is qualified |
5 | XOSCDLFIM | R/W | 1h | 0: Disable interrupt generation when XOSCDLF is qualified 1: Enable interrupt generation when XOSCDLF is qualified |
4 | XOSCLFIM | R/W | 1h | 0: Disable interrupt generation when XOSCLF is qualified 1: Enable interrupt generation when XOSCLF is qualified |
3 | RCOSCDLFIM | R/W | 0h | 0: Disable interrupt generation when RCOSCDLF is qualified 1: Enable interrupt generation when RCOSCDLF is qualified |
2 | RCOSCLFIM | R/W | 1h | 0: Disable interrupt generation when RCOSCLF is qualified 1: Enable interrupt generation when RCOSCLF is qualified |
1 | XOSCHFIM | R/W | 1h | 0: Disable interrupt generation when XOSCHF is qualified 1: Enable interrupt generation when XOSCHF is qualified |
0 | RCOSCHFIM | R/W | 0h | 0: Disable interrupt generation when RCOSCHF is qualified 1: Enable interrupt generation when RCOSCHF is qualified |
OSCRIS is shown in Table 7-79.
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Oscillator Raw Interrupt Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | HFSRCPENDRIS | R | 0h | SCLK_HF source switch pending interrupt. After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source change request, then the requested SCLK_HF source will be enabled and qualified. When the new source is ready to be used as a clock source, then the interrupt HSSRCPENDRIS will go high. When the Flash allows SCLK_HF source switching to take place after flash memory read access is disabled. At this time the actual SCLK_HF clock source switch will be performed, and the interrupt status HSSRCPENDRIS will go low. 0: Indicates SCLK_HF source is not ready to be switched 1: Indicates SCLK_HF source is ready to be switched Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.HFSRCPENDC |
6 | LFSRCDONERIS | R | 0h | SCLK_LF source switch done. The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that the SCLK_LF source shall be changed. After an SCLK_LF clock source change is requested, the new source may need to be enabled and qualified before switching of clock source can be done. The interrupt LFRSRCDONERIS goes high to indicate that the SCLK_LF clock source switching has been performed. LFRSRCDONERIS will go low again when the next clock source change is requested by writing to DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL . 0: Indicates SCLK_LF source switch has not completed 1: Indicates SCLK_LF source switch has completed Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.LFSRCDONEC |
5 | XOSCDLFRIS | R | 0h | The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When XOSCDLFRIS is high, XOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have XOSC_HF selected as clock source, the XOSC_HF source is automatically disabled and the XOSCDLFRIS interrupt status will go low. 0: XOSCDLF has not been qualified 1: XOSCDLF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCDLFC |
4 | XOSCLFRIS | R | 0h | The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator has been qualified with respect to frequency. The XOSCLFRIS interrupt status goes high when the XOSC_LF oscillator is ready to be used as a clock source. After the clock qualification is successful, XOSCLFRIS interrupt status remains high, and further qualification is turned off until the XOSC_LF oscillator is disabled. XOSCLFRIS interrupt status will go low only at initial power-on, or after the XOSC_LF oscillator has been disabled when being deselected as a clock source. 0: XOSCLF has not been qualified 1: XOSCLF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCLFC |
3 | RCOSCDLFRIS | R | 0h | The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. When RCOSCDLFRIS is high, RCOSC_HF will be used as source for SCLK_LF when selected. When none of the system clocks have RCOSC_HF selected as clock source, the RCOSC_HF source is automatically disabled and the RCOSCDLFRIS interrupt status will go low. If the SCLK_LF or ACLK_REF source is changed from RCOSC_HF derived to XOSC_HF derived low-frequency clock and the new source has not been qualified, then the clock will remain running on the original source. The RCOSCDLFRIS interrupt will then remain high. 0: RCOSCDLF has not been qualified 1: RCOSCDLF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCDLFC |
2 | RCOSCLFRIS | R | 0h | The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF oscillator has been qualified with respect to frequency. The RCOSCLFRIS interrupt status goes high when the RCOSC_LF oscillator is ready to be used as a clock source. After the clock qualification is successful, RCOSCLFRIS interrupt status remains high, and further qualification is turned off until the RCOSC_LF oscillator is disabled. RCOSCLFRIS interrupt status will go low only at initial power-on, or after the RCOSC_LF oscillator has been disabled when being deselected as a clock source. 0: RCOSCLF has not been qualified 1: RCOSCLF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCLFC |
1 | XOSCHFRIS | R | 0h | The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been qualified for use as a clock source. XOSCHFRIS is also used in TCXO mode (when DDI_0_OSC:XOSCHFCTL.TCXO_MODE is 1). When the XOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The XOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source. 0: XOSC_HF has not been qualified 1: XOSC_HF has been qualified Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.XOSCHFC |
0 | RCOSCHFRIS | R | 0h | The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been qualified for use as a clock source When the RCOSCHFRIS interrupt is high, the oscillator is qualified and will be used as a clock source when selected. The RCOSCHFRIS interrupt goes low when the oscillator is disabled after being deselected as a clock source. 0: RCOSC_HF has not been qualified 1: RCOSC_HF has been qualified Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of qualifying raw interrupt and enable of interrupt mask is indifferent for generating an OSC Interrupt. Set by HW. Cleared by writing to OSCICR.RCOSCHFC |
OSCICR is shown in Table 7-80.
Return to the Summary Table.
Oscillator Raw Interrupt Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7 | HFSRCPENDC | W | 0h | Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 has no effect. |
6 | LFSRCDONEC | W | 0h | Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 has no effect. |
5 | XOSCDLFC | W | 0h | Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 has no effect. |
4 | XOSCLFC | W | 0h | Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 has no effect. |
3 | RCOSCDLFC | W | 0h | Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 has no effect. |
2 | RCOSCLFC | W | 0h | Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 has no effect. |
1 | XOSCHFC | W | 0h | Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 has no effect. |
0 | RCOSCHFC | W | 0h | Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 has no effect. |
NVMNSCADDR is shown in Table 7-81.
Return to the Summary Table.
NVM Non-Secure Callable boundary Address
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R | 0h | Register parity bit. |
30-20 | RESERVED | R | 0h | Reserved |
19-10 | BOUNDARY | R/W | 0h | Non-Secure callable boundary address. Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
9-0 | RESERVED | R | 0h | Reserved |
NVMNSADDR is shown in Table 7-82.
Return to the Summary Table.
NVM Non-Secure boundary Address
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R | 1h | Register parity bit |
30-21 | RESERVED | R | 0h | Reserved |
20 | BOUNDARY_MSB | R | 1h | Non-Secure boundary address MSB HW controlled. |
19-13 | BOUNDARY | R/W | 0h | Non-Secure boundary address. Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
12-0 | RESERVED | R | 0h | Reserved |
SRAMNSCADDR is shown in Table 7-83.
Return to the Summary Table.
SRAM Non-Secure Callable boundary Address
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R | 0h | Register parity bit |
30-19 | RESERVED | R | 0h | Reserved |
18-10 | BOUNDARY | R/W | 0h | Non-Secure callable boundary address. Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
9-0 | RESERVED | R | 0h | Reserved |
SRAMNSADDR is shown in Table 7-84.
Return to the Summary Table.
SRAM Non-Secure Callable boundary Address
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R | 0h | Register parity bit |
30-19 | RESERVED | R | 0h | Reserved |
18-10 | BOUNDARY | R/W | 120h | Non-Secure boundary address. Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
9-0 | RESERVED | R | 0h | Reserved |
BUSSECCFG is shown in Table 7-85.
Return to the Summary Table.
BUS Security Configuration Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | VALID | R/W | 0h | Security configuration valid Registers that needs to be followed by VALID before settings being applied are: - NVMNSCADDR - NVMNSADDR - SRAMNSCADDR - SRAMNSADDR - BUSSECCFG - CPULOCK |
30-8 | RESERVED | R | 0h | Reserved |
7-0 | BUS_CFG | R/W | FFh | Bus interconnect security and firewall configuration 0xFF : Trustzone enabled 0xF9 : Trustzone disabled Others: Reserved. Software should not rely on the value of reserved and should not write reserved settings. |
CPULOCK is shown in Table 7-86.
Return to the Summary Table.
CPU Lock Register
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PARITY | R | 1h | Register parity bit |
30-5 | RESERVED | R | 0h | Reserved |
4 | LOCKNSVTOR | R/W | 1h | When set will lock non-secure vector table base address Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
3 | LOCKSVTAIRCR | R/W | 1h | When set will lock - Secure vector table base address - Secure interrupt priority - Busfault - Hardfault NMI security target Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
2 | LOCKSAU | R/W | 1h | When set will lock SAU regions Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
1 | LOCKNSMPU | R/W | 1h | When set will lock non-secure MPU Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |
0 | LOCKSMPU | R/W | 1h | When set will lock secure MPU Writing this field when BUSSECCFG.VALID is set may result in undefined behavior. |