SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-190 lists the memory-mapped registers for the CPU_TPIU registers. All register offset addresses not listed in Table 2-190 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | SSPSR | Supported Sync Port Sizes | Section 2.5.11.1 |
4h | CSPSR | Current Sync Port Size | Section 2.5.11.2 |
10h | ACPR | Async Clock Prescaler | Section 2.5.11.3 |
F0h | SPPR | Selected Pin Protocol | Section 2.5.11.4 |
300h | FFSR | Formatter and Flush Status | Section 2.5.11.5 |
304h | FFCR | Formatter and Flush Control | Section 2.5.11.6 |
308h | PSCR | Formatter Synchronization Counter | Section 2.5.11.7 |
FA0h | CLAIMMASK | Claim Tag Mask | Section 2.5.11.8 |
FA0h | CLAIMSET | Claim Tag Set | Section 2.5.11.9 |
FA4h | CLAIMTAG | Current Claim Tag | Section 2.5.11.10 |
FA4h | CLAIMCLR | Claim Tag Clear | Section 2.5.11.11 |
FC8h | DEVID | Device ID | Section 2.5.11.12 |
FCCh | DEVTYPE | The Device Type Identification | Section 2.5.11.13 |
Complex bit access types are encoded to fit into small table cells. Table 2-191 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
SSPSR is shown in Table 2-192.
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Supported Sync Port Sizes
This register represents a single port size that is supported on the device, that is, 4, 2 or 1. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
3 | FOUR | R | 1h | 4-bit port size support 0x0: Not supported 0x1: Supported |
2 | THREE | R | 0h | 3-bit port size support 0x0: Not supported 0x1: Supported |
1 | TWO | R | 1h | 2-bit port size support 0x0: Not supported 0x1: Supported |
0 | ONE | R | 1h | 1-bit port size support 0x0: Not supported 0x1: Supported |
CSPSR is shown in Table 2-193.
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Current Sync Port Size
This register has the same format as SSPSR but only one bit can be set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported can cause Unpredictable behavior. On reset this defaults to the smallest possible port size, 1 bit.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
3 | FOUR | R/W | 0h | 4-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. |
2 | THREE | R/W | 0h | 3-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. |
1 | TWO | R/W | 0h | 2-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. |
0 | ONE | R/W | 1h | 1-bit port enable Writing values with more than one bit set in CSPSR, or setting a bit that is not indicated as supported in SSPSR can cause Unpredictable behavior. |
ACPR is shown in Table 2-194.
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Async Clock Prescaler
This register scales the baud rate of the asynchronous output.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
12-0 | PRESCALER | R/W | 0h | Divisor for input trace clock is (PRESCALER + 1). |
SPPR is shown in Table 2-195.
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Selected Pin Protocol
This register selects the protocol to be used for trace output.
Note: If this register is changed while trace data is being output, data corruption occurs.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1-0 | PROTOCOL | R/W | 1h | Trace output protocol
0h = TracePort mode 1h = SerialWire Output (Manchester). This is the reset value. 2h = SerialWire Output (NRZ) |
FFSR is shown in Table 2-196.
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Formatter and Flush Status
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
3 | FTNONSTOP | R | 1h | 0: Formatter can be stopped 1: Formatter cannot be stopped |
2 | TCPRESENT | R | 0h | This field always reads as zero |
1 | FTSTOPPED | R | 0h | This field always reads as zero |
0 | FLINPROG | R | 0h | Read only. Flush in progress. Value can be: 0x0 When all the data received, before the flush is acknowledged, has been output on the trace port 0x1 When a flush is initiated. |
FFCR is shown in Table 2-197.
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Formatter and Flush Control
When one of the two single wire output (SWO) modes is selected, ENFCONT enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended to be used when it is necessary to connect a device containing an ETM to a trace capture device that is only able to capture Serial Wire Output (SWO) data. Enabling or disabling the formatter causes momentary data corruption.
Note: If the selected pin protocol register (SPPR.PROTOCOL) is set to 0x00 (TracePort mode), this register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire modes is then selected, the register reverts to its previously programmed value.
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
8 | TRIGIN | R/W | 1h | Indicates that triggers are inserted when a trigger pin is asserted. |
7 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
6 | FONMAN | R/W | 1h | Flush on manual. Value can be: 0x0 When the flush completes. Set to 0 on a reset of the TPIU. 0x1 Generates a flush. |
5-2 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
1 | ENFCONT | R/W | 1h | Enable continuous formatting: 0: Continuous formatting disabled 1: Continuous formatting enabled |
0 | RESERVED | R/W | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
PSCR is shown in Table 2-198.
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Formatter Synchronization Counter
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
4-0 | PSCOUNT | R/W | 0h | Periodic Synchronization Count. Determines the reload value of the Periodic Synchronization Counter. The reload value takes effect the next time the counter reaches zero. Reads from this register return the reload value programmed into this register 0b00000 Synchronization disabled. 0b00111 128 bytes. 0b01000 256 bytes. 0b11111 231 bytes. |
CLAIMMASK is shown in Table 2-199.
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Claim Tag Mask
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLAIMMASK | R | Fh | This register forms one half of the Claim Tag value. When reading this register returns the number of bits that can be set (each bit is considered separately): 0: This claim tag bit is not implemented 1: This claim tag bit is implemented The behavior when writing to this register is described in CLAIMSET. |
CLAIMSET is shown in Table 2-200.
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Claim Tag Set
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLAIMSET | W | Fh | This register forms one half of the Claim Tag value. Writing to this location allows individual bits to be set (each bit is considered separately): 0: No effect 1: Set this bit in the claim tag The behavior when reading from this location is described in CLAIMMASK. |
CLAIMTAG is shown in Table 2-201.
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Current Claim Tag
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLAIMTAG | R | 0h | This register forms one half of the Claim Tag value. Reading this register returns the current Claim Tag value. Reading CLAIMMASK determines how many bits from this register must be used. The behavior when writing to this register is described in CLAIMCLR. |
CLAIMCLR is shown in Table 2-202.
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Claim Tag Clear
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | CLAIMCLR | W | 0h | This register forms one half of the Claim Tag value. Writing to this location enables individual bits to be cleared (each bit is considered separately): 0: No effect 1: Clear this bit in the claim tag. The behavior when reading from this location is described in CLAIMTAG. |
DEVID is shown in Table 2-203.
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Device ID
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | DEVID | R | CA0h | This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no ETM present. |
DEVTYPE is shown in Table 2-204.
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The Device Type Identification
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
7-4 | SUBTYPE | R | 1h | Identifies the classification of the debug component |
3-0 | MAJORTYPE | R | 1h | Indicates this device is a trace sink and specifically a TPIU |