SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Table 2-84 lists the memory-mapped registers for the CPU_SYSTICK registers. All register offset addresses not listed in Table 2-84 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CSR | Controls the SysTick timer and provides status data `FTSSS | Section 2.5.3.1 |
4h | RVR | Provides access SysTick timer counter reload value `FTSSS | Section 2.5.3.2 |
8h | CVR | Reads or clears the SysTick timer current counter value `FTSSS | Section 2.5.3.3 |
Ch | CALIB | Reads the SysTick timer calibration value and parameters `FTSSS | Section 2.5.3.4 |
Complex bit access types are encoded to fit into small table cells. Table 2-85 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CSR is shown in Table 2-86.
Return to the Summary Table.
Controls the SysTick timer and provides status data `FTSSS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
16 | COUNTFLAG | R/W | 0h | Indicates whether the counter has counted to zero since the last read of this register |
15-3 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
2 | CLKSOURCE | R/W | 0h | Indicates the SysTick clock source |
1 | TICKINT | R/W | 0h | Indicates whether counting to 0 causes the status of the SysTick exception to change to pending |
0 | ENABLE | R/W | 0h | Indicates the enabled status of the SysTick counter |
RVR is shown in Table 2-87.
Return to the Summary Table.
Provides access SysTick timer counter reload value `FTSSS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
23-0 | RELOAD | R/W | 0h | The value to load into the SYST_CVR `FTSSS when the counter reaches 0 |
CVR is shown in Table 2-88.
Return to the Summary Table.
Reads or clears the SysTick timer current counter value `FTSSS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
23-0 | CURRENT | W | 0h | Writing any value clears the SysTick timer counter `FTSSS to zero |
CALIB is shown in Table 2-89.
Return to the Summary Table.
Reads the SysTick timer calibration value and parameters `FTSSS
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | NOREF | R | 0h | Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented |
30 | SKEW | R | 0h | Indicates whether the 10ms calibration value is exact |
29-24 | RESERVED | R | 0h | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
23-0 | TENMS | R | 0h | Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If this field is zero, the calibration value is not known |