SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
AUX_DDI0_OSC (listed in Table 20-19) is not really a digital peripheral. As shown in Figure 20-1, both the System CPU and the Sensor Controller access DDI_0_OSC through the AUX_DDI0_OSC module to control and configure the system clocks. The AUX_DDI0_OSC module supports four different types of accesses to provide efficiency as it connects to the analog domain over a multicycle bus interface. The access types are:
The Sensor Controller detects less access latency when the bus clock rate is higher than the SCE clock rate.
If the System CPU application requires access to this module, the application must use the TI provided DriverLib API functions. Sensor Controller Studio API functions includes access when necessary and the user need not consider this module when developing code.
For system clock description, see Section 20.2.
As noted in Section 20.3.2.2, SCE access to AUX_DDI0_OSC is restricted when device interconnect and firewall is configured to normal or contingency 1 modes, i.e. whenever PRCM:BUSSECCFG.BUS_CFG takes values other than 0xF9 and 0xF3. In this case, SCE may only access DDI half-words specified by AUX_SCE:NONSECDDIACC0-3. Other accesses will be blocked and SCE suspended.