SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Figure 23-4 and Figure 23-5 show single and continuous transmission signal sequences for Motorola SPI format with SPO = 0 and SPH = 0, respectively.
In this configuration, the following occurs during idle periods:
If the SPI is enabled and valid data is in the TX FIFO, the SPIn_CS master signal is driven low at the start of transmission which causes enabling of slave data onto the SPIn_MISO input line of the master. The master SPIn_MOSI output is enabled.
One-half SPIn_CLK period later, valid master data is transferred to the SPIn_MOSI pin. Once both the master and slave data are set, the SPIn_CLK master clock pin goes high after an additional one-half SPIn_CLK period.
The data is now captured on the rising edges and propagated on the falling edges of the SPIn_CLK signal.
For a single-word transmission after all bits of the data word are transferred, the SPIn_CS line is returned to its IDLE high state one SPIn_CLK period after the last bit is captured.
For continuous back-to-back transmissions, the SPIn_CS signal must pulse high between each data word transfer because the slave-select pin freezes the data in its serial peripheral register and does not allow altering of the data if the SPH bit is clear. The master device must raise the SPIn_CS pin of the slave device between each data transfer to enable the serial peripheral data write. When the continuous transfer completes, the SPIn_CS pin is returned to its IDLE state one SPIn_CLK period after the last bit is captured.