SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
All exceptions have an assigned priority that is used to control both pre-emption and prioritization between pending exceptions. A lower priority value indicates a higher priority. You can configure priorities for all exceptions except Reset, HardFault, and NMI.
If software does not configure any priorities, then all exceptions with a configurable priority have a priority of 0.
Configurable priorities are in the range 0-255. The Reset, HardFault, and NMI exceptions, with fixed negative priority values always have higher priority than any other exception.
For configurable priority exceptions, the target Security state alsoaffects the programmed priority. Depending on the value of CPU_SCB:AIRCR.PRIS, the priority can be extended
In Table 5-3, the values in columns 2 and 3 must match, and increase from zero in increments of 32. The values in column 4 start from 128 and increase in increments of 16.
Priority Value [7:5] | Secure Priority | Non-secure priority when CPU_SCB:AIRCR.PRIS = 0 | Non-secure priority when CPU_SCB:AIRCR.PRIS = 1 |
---|---|---|---|
0 | 0 | 0 | 128 |
1 | 32 | 32 | 144 |
2 | 64 | 64 | 160 |
3 | 96 | 96 | 176 |
4 | 128 | 128 | 192 |
5 | 160 | 160 | 208 |
6 | 192 | 192 | 224 |
7 | 224 | 224 | 240 |
If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1].
When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs. If an exception occurs with the same priority as the exception being handled, the handler is not preempted, irrespective of the exception number. However, the status of the new interrupt changes to pending.