SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
When the clock loss feature is enabled with the DDI_0_OSC:CTL0.CLK_LOSS_EN and the AON_PMCTL:RESETCTL.CLK_LOSS_EN registers, a detected loss of SCLK_LF, SCLK_MF, or SCLK_HF results in a system reset. After recovery, the AON_PMCTL:RESETCTL.RESET_SRC register shows clock loss as the source of reset.
The application must set both DDI_0_OSC:CTL0.CLK_LOSS_EN and the AON_PMCTL:RESETCTL.CLK_LOSS_EN in order to enable Clock Loss Detection, it is not enabled after boot.