SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Each data frame is between 4 and 32 bits long, depending on the size of data programmed. The control bit SPI:CTL1.MSB field can be programmed to define the direction of the data input and output as most-significant-bit (MSB) or least-significant-bit (LSB) first. If parity is enabled, the parity bit is always received as the last bit.
With the control register bits SPI:CTL0.DSS, the bit length per transfer is defined between 4 – 32 bits for master mode and 7 – 32 bits for slave mode.