SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The following software example in pseudocode describes the actions that are typically executed by the host software. The example starts the Hash engine with a new Hash session that receives the input data through the DMA interface. In the end, the intermediate digest (nonfinal Hash operation) or the finalized Hash digest (final Hash operation) is read as a result digest through the slave interface.
// configure master control module
write ALGSEL 0x00000008 // enable DMA path to the SHA-2 engine
write IRQCLR 0x00000001 // clear any outstanding events
// configure hash engine
write HASHMODE = 0x00000021 // indicate the start of a new hash session and SHA512
write HASHINLENL // write the length of the message (lo)
write HASHINLENH // write the length of the message (hi)
// if the final digest is required (pad the input DMA data), write the following register
write HASHIOBUFCTRL = 0x80 // pad the data that is transferred via DMA
// configure DMAC
write DMACH0CTL 0x000000001 // enable DMA channel 0 for message data
write DMACH0EXTADDR <ext_memory_address> // base address of the data in ext. memory
write DMACH0LEN <length> // input data in bytes, equal to the message length
wait IRQSTAT[0] = '1' // wait for operation done (hash and DMAC are ready)
check IRQSTAT[31] == '0' // check for the absence of errors
// read digest
read HASHDIGESTA
...
read HASHDIGESTP
// acknowledge result and clear interrupts
write HASHIOBUFCTRL = 0x00000001 // acknowledge reading of the digest
write IRQCLR 0x00000001 // clear the interrupt
write ALGSEL 0x00000000 // disable the master control/DMA clock
// end of algorithm