SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The following software example in pseudo code, describes the actions that are typically executed by the Host software to authenticate a message, stored in external memory, with AES-CBC-MAC mode. The result TAG is read via the slave interface. The packet is divided into two parts: part 1 and part 2. The length of part 1 must be multiples of the block size.
// configure the master control module
write ALGSEL 0x00000002 // enable the DMA path to the AES engine
write IRQCLR 0x00000001 // clear any outstanding events
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x00000000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31] == ’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’ // check that the key is loaded without errors
// write the initialization vector
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0000_0000_1000_0000_0000_1100 // program AES-CBC-MAC-128 authentication
write AESDATALEN0 // write length of the crypto block part 1 (lo)
write AESDATALEN1 // write the length of the crypto block part 1 (hi)
// (must be block size aligned)
// configure DMAC
write DMACH0CTRL 0x000000001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the input data in ext. memory
write DMACH0DMALENGTH <length> // input data length in bytes, equal to the
// message part 1 length (must be block size aligned)
// wait for completion
wait IRQSTAT[0] == ’1’ // wait for operation completed
check IRQSTAT[31] == ‘0’ // check for the absence of errors
write ALGSEL 0x00000000 // disable master control/DMA clock
// read intermediate tag
wait AESCTL[30] == ’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT_0
...
read AESTAGOUT_3 // this read clears the SAVED_CONTEXT_RDY flag
// configure the master control module
write ALGSEL 0x00000002 // enable the DMA path to the AES engine
write IRQCLR 0x00000001 // clear any outstanding events
// configure the key store to provide a pre-loaded AES key
write KEYREADAREA 0x00000000 // load the key from ram area 0 (NOTE: The key
// must be pre-loaded to this area)
wait KEYREADAREA[31] == ’0’ // wait until the key is loaded to the AES module
check IRQSTAT[29] = ‘0’ // check that the key is loaded without errors
// write the intermediate tag to IV
write AESIV_0
...
write AESIV_3
// configure the AES engine
write AESCTL = 0b0010_0000_0000_0000_1000_0000_0000_1100 // program AES-CBC-MAC-
// 128 authentication
write AESDATALEN0 // write length of the crypto block part 2 (lo)
write AESDATALEN1 // write the length of the crypto block part 2 (hi)
// (may be non-block size aligned)
// configure DMAC
write DMACH0CTRL 0x000000001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the input data in ext. memory
write DMACH0DMALENGTH <length> // input data length in bytes, equal to
// the message part 2 length (may be
// non-block size aligned)
// wait for completion
wait IRQSTAT[0] == ’1’ // wait for operation completed
check IRQSTAT[31] == ‘0’ // check for the absence of errors
write ALGSEL 0x00000000 // disable master control/DMA clock
// read final tag
wait AESCTL[30] == ’1’ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT_0
...
read AESTAGOUT_3 // this read clears the SAVED_CONTEXT_RDY flag
// end of algorithm