In the CC13x4x10 and
CC26x4x10 device platform, the JTAG subsystem implements two IEEE standards for debug and test purposes:
- IEEE standard 1149.1: Standard Test Access Port and Boundary Scan Architecture Test Access Port (TAP) [JTAG 1]. This standard is known by the acronym JTAG.
- Class 4 IEEE 1149.7: Standard for Reduced-pin and Enhanced-functionality Test Access Port and Boundary-scan Architecture [JTAG 2]. This is known by acronym cJTAG (compact JTAG). This standard serializes the IEEE 1149.1 transactions using a variety of compression formats to reduce the number of pins needed to implement
a JTAG debug port.
The JTAG interface is used for the following:
- Flash programming
- Debug access
- Test / Boundary Scan
- Power Profiling
The JTAG subsystem also implements a firewall for unauthorized access to debug/test ports. Figure 6-1 shows a block diagram of the JTAG subsystem.
The IEEE 1149.1 TAP uses the following signals to support the operation:
- TCK (Test Clock): This signal synchronizes the internal state machine operations.
- TMS (Test Mode Select): This signal is sampled at the rising edge of TCK to determine the next state.
- TDI (Test Data In): This signal represents the data shifted into the test or programming logic of the device. TDI is sampled at the rising edge of TCK when the internal state machine is in the correct state.
- TDO (Test Data Out): This signal represents the data shifted out of the test or programming logic of the device and is valid on the falling edge of TCK when the internal state machine is in the correct state.
There is no dedicated I/O pin for TRST. The JTAG subsystem is reset with system-wide resets and power-on reset.