SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
Figure 23-6 shows the transfer signal sequence for Motorola SPI format with SPO = 0 and SPH = 1, which covers both single and continuous transfers.
In this configuration, the following occurs during idle periods:
If the SPI is enabled and valid data is in the TX FIFO, the SPIn_CS master signal goes low at the start of transmission. The master SPIn_MOSI output is enabled. After an additional one-half SPIn_CLK period, both master and slave valid data are enabled onto their respective transmission lines. At the same time, SPIn_CLK is enabled with a rising-edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SPIn_CLK signal.
For a single-word transfer, after all bits are transferred, the SPIn_CS line is returned to its IDLE high state one SPIn_CLK period after the last bit is captured.
For continuous back-to-back transfers, the SPIn_CS pin is held low between successive data words and terminates like a single-word transfer.