SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The AON IOC contains the output enable control for the 32 kHz LF system clock (SCLK_LF) output, and the clock signal has its own PORT_ID called AON_CLK32K (0x7). This makes it easy to output the clock signal to a pin. Map the clock to a chosen DIO, and enable the clock output by setting the AON_IOC:CLK32KCTL.OE_N register field to 0x0. The following code snippets show how this can be done:
#include <ti/devices/DeviceFamily.h>
#include DeviceFamily_constructPath(driverlib/aon_ioc.h)
GPIO_setMux(CONFIG_GPIO_x, IOC_PORT_AON_CLK32K); // CONFIG_GPIO_x is assigned
// DIO through SysConfig
AONIOC32kHzOutputEnable();
This outputs the LF system clock signal in all power modes except for Shutdown.
The AON_CLK32K PORT_ID value is also chosen when using a DIO as the input source for the 32 kHz LF system clock. For a description of how to use a DIO as the clock source, see Chapter 170.
The AON_CLK32K PORT_ID must be used as only a single clock output or as only a clock input.