SWCU194 March 2023 CC1314R10 , CC1354P10 , CC1354R10 , CC2674P10 , CC2674R10
The AUX Timer2 is asynchronous to the AUX clock. It is accessed over an asynchronous bus bridge. The master side is clocked by the AUX bus clock, and the slave side is clocked by the Timer2 clock. The bridge has a single write buffer. An ongoing bus transfer stalls a new access, until the former completes.
To minimize access latency, TI recommends setting the Timer2 clock frequency to AUX clock frequency or higher during configuration.