SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

5.1 Configuration of Devices

The AWR2243 devices in a cascaded chip system need to be configured as either MULTICHIP_MASTER or MULTICHIP_SLAVE. This can be done through the message AWR_CHAN_CONF_SET_SB. Note that the message allows a SINGLECHIP option, typically applicable only to single chip systems.

Only one AWR2243 device should be configured as MULTICHIP_MASTER. This AWR2243 device is the master chip and generates FMCW LO and conveys to other MULTICHIP_SLAVE AWR2243 devices in the cascaded chip system.

Typically, the MULTICHIP_MASTER’s DIG_SYNC_OUT pin is connected to the DIG_SYNC_IN pins of all the AWR2243 devices in the cascaded chip system. This allows the timing of chirps to be synchronous across the AWR2243 devices.