SWRA679 January   2021 CC3200 , CC3220R , CC3220S , CC3220SF , CC3230S , CC3230SF , CC3235S , CC3235SF

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Basics of the SAR ADC Architecture
    2. 1.2 Introduction to the CC32XX ADC
      1. 1.2.1 Main Features
      2. 1.2.2 ADC Sampling Operation
      3. 1.2.3 ADC Additional Information
  3. 2ADC Application Examples
    1. 2.1 Battery Voltage Measurements
      1. 2.1.1 Important Considerations
        1. 2.1.1.1 Extra Current Draw
        2. 2.1.1.2 Droop Correction
        3. 2.1.1.3 Offset Adjustment
        4. 2.1.1.4 Least Squares Fit
        5. 2.1.1.5 Choosing the Capacitor (for droop correction)
        6. 2.1.1.6 First Measurement
        7. 2.1.1.7 Time Between Measurements
  4. 3AC Measurements
  5. 4Useful References
    1. 4.1 Smart Thermostat
    2. 4.2 Measuring Air Quality With the Winsen MP503 Analog Sensor
    3. 4.3 Touch Position Detection With HMI Through Resistive Touchscreen
  6. 5References

1.2.1 Main Features

The CC32xx provides a general purpose, multi-channel Analog-to-Digital Converter (ADC). Each of the ADC channels supports 12-bit conversion resolution with sampling periodicity of 16 uS (62.5 Ksps/channel). Each channel has an associated FIFO and DMA. For detailed electrical characteristics of the ADC, refer to the CC3200 data sheet (SWAS032).

  • Total of 8 channels:
    • 4 external analog input channels for user applications
    • 4 internal channels reserved for SimpleLink subsystem (network and Wi-Fi).
  • 12-bit resolution
  • Fixed sampling rate of 16 μs per channel. Equivalent to 62.5K samples/sec per channel
  • Fixed round-robin sampling across all channels
  • Samples are uniformly spaced and interleaved. Multiple user channels can be combined together to realize higher sampling rate. For example, all four channels can be shorted together to get an aggregate sampling rate of 250K samples/sec.
  • DMA interface to transfer data to the application RAM; dedicated DMA channel for each channel.
  • Capability to timestamp ADC samples using 17-bit timer running on a 40-MHz clock. The user can read the timestamp along with the sample from the FIFO registers. Each sample in the FIFO contains actual data and a timestamp.
GUID-20201021-CA0I-44VK-NQNP-F2LCWN2MBKL4-low.gif Figure 1-2 Architecture of the ADC Module in CC32xx