SWRA680 November 2020 CC3100 , CC3120 , CC3135 , CC3200 , CC3220R , CC3220S , CC3220SF , CC3235S , CC3235SF
The layout of the crystal can reduce the parasitic capacitance and, more importantly, reduce noise from coupling on the input of the oscillators. Noise on the input of the oscillator can lead to severe side effects such as clock glitches, flash corruption, or system crashes because the CC31xx and CC32xx devices rely on the crystal oscillators for the systems fast and slow clock.
The following are a few general recommendations for the layout of the crystals:
Figure 5-1 shows the top layer of the layout of the CC32xx reference design. The bottom layer is a solid ground plane. For more details, see the CC3235S/CC3235SF SimpleLink™ Wi-Fi® LaunchPad™ Design Files, see [12]. The same crystal layout can be used with CC31xx device.