The Direct Sequence Spreader assigns a known bit pattern to each of the incoming bits to the module. It can be considered a form of repetition code where a bit of duration t is replaced by M bits each of duration T_b. As a consequence, the rate at which information is transmitted is reduced by 1/M. If you want to keep information rate constant, then the bit duration must be reduced by T_b/M, which subsequently increases the bandwidth by factor M. As a consequence the information bits are “chipped” into smaller duration symbols and are transmitted over the air. The ratio of symbol rate to the bit rate is called processing gain of a spread spectrum system.

The processing gain is the figure of merit that is considered when comparing narrow-band system to spread spectrum application. To appreciate intuitively how this improves the error performance we consider the slicer in a correlation receiver followed by a maximum likelihood (ML) decision block. In a DSSS system the block will make decisions on each symbol and then integrate the result over one information bit period. The probability of making a bit error therefore reduces when the bit is divided into many short duration symbols.

In the CC1352 DSSS modes, the spreader length can be configured to be 1, 2, 4, and 8. Table 2-1 illustrates the bit mapping for each of the options.

The WB-DSSS scheme is implemented as 2-GFSK PHY with over the air symbol rate of 480 kbps.