SWRA754 april   2023 AWRL6432 , IWRL6432

 

  1.   Trademarks
  2. 1Power Management Framework
  3. 2Hardware Design Options for Low Power
  4. 3Chirp Design Optimizations for Low Power
  5. 4Reducing Power in the Interframe Idle and Deep Sleep States
  6. 5Measuring Power
  7. 6References
  8. 7Revision History

Hardware Design Options for Low Power

The xWRL6432 device is designed to be powered by a Power Management Integrated Circuit (PMIC) or discrete power supply solutions. Between 1-3 different supply voltage rails can be provided to the xWRL6432. This flexibility enables systems to be tailored to reduce power usage or BOM cost. When the device boots, it senses the number of input voltages provided, and adjusts its internal circuitry accordingly. The table below (with images taken from [1]) shows the four topologies that can be used to supply the power rails to the xWRL6432.

1.8 V IO Mode3.3 V IO Mode
Power OptimizedGUID-20230406-SS0I-5KRX-FCD2-SDF2JRNWC0DQ-low.svg

Number of power supply rails needed : 2


Lowest Power Topology
GUID-20230406-SS0I-BHGP-CHPT-Q94VBGJNJDFJ-low.svg

Number of power supply rails needed : 3

BOM OptimizedGUID-20230406-SS0I-CF1Z-RWTG-G6T7L8MS0JXV-low.svg

Number of power supply rails needed : 1


Lowest Cost Topology
GUID-20230406-SS0I-V5PT-M6XS-PLTFXHT5SF2M-low.svg

Number of power supply rails needed : 2

The four topologies vary on two dimensions: IO voltage and the source of the 1.2 V power supply. The IOs on the device can run on either 3.3 V logic or 1.8 V logic depending on the application requirements. The 1.2 V power supply can be generated internally through a low dropout regulator (LDO) that generates it from a 1.8 V supply (BOM-Optimized Modes), or it can be provided to the device using an external voltage source (Power Optimized Modes).